1. A wireless communications system which uses at least two kinds of wireless communication networks, enables to simultaneously connect to a basic access network for executing signaling communication in which communication is controlled so as to be continuously switched and to a wireless access network for executing data communications other than the signaling communication and comprises wireless communication terminals and a wireless communication server, characterized in that:
each of the wireless communication terminals comprises a seamless application processing unit for executing connection processing to the basic access network and connectiondisconnection processing to and from the wireless access network, an audio application processing unit for transmitting and receiving audio data though the wireless access network, a video application processing unit for transmitting and receiving video data through the wireless access network, a client processing unit having a client function in the signaling communication for controlling the audio application and the video application, a multicast communication node application processing unit for setting multicast reception using at least the two kinds of the wireless communication networks, respective network devices corresponding to the respective wireless communication networks, and position obtaining means of the wireless communication terminals; and
the wireless communication server comprises a home agent application processing unit for setting a multicast transmission using at least the two kinds of the wireless communication networks, a basic access network server processing unit for notifying, when the wireless communication networks are continuously switched, the wireless communication terminals of a wireless communication network acting as a switching candidate and managing the signaling communication for communicating the status of the respective wireless communication terminals therebetween and managing the registrationupdate processing of the respective wireless communication terminals, a relay server processing unit for managing relay of the signaling communication for communicating the status of the respective wireless communication terminals therebetween, a terminal status table for managing the status of the respective wireless communication terminals, and a terminal configuration table for managing the wireless communication networks implemented in the wireless communication terminals,
wherein the seamless application processing unit obtains position information from the position obtaining means and notifies the basic access network server processing unit of the position information, and the basic access network server processing unit registers the position information to the terminal status table.
2. A wireless communications system according to claim 1, wherein, in the wireless communication terminals, the seamless application processing unit monitors the connection status of the respective wireless communication networks at a predetermined cycle based on a list of the wireless communication networks previously recorded to the wireless communication terminals.
3. The wireless communications system according to claim 1 or 2, characterized in that:
the wireless communication server comprises two servers of,
a home agent server comprising the home agent application processing unit and a resource server comprising the basic access network server processing unit, the basic access network server processing unit, the relay server processing unit, the terminal status table, and the terminal configuration table,
wherein, the home agent server is provided with a proxy server processing unit for relaying communication between the seamless application processing unit and the basic access network server processing unit.
4. A wireless communications system according to claim 1, wherein:
the wireless communication terminals are registered to the relay server processing unit together with the position information thereof; and
each of respective client processing units transmits a subscribe request signal to an opponent client processing unit between two optional registered wireless communication terminals and the client processing unit which receives the subscribe request signal directly responds its information to an opponent and establishes connection between the wireless communication terminals.
5. A wireless communications system according to claim 4, wherein the audio application processing unit and the video application processing unit establish direct connection to the audio application processing unit and the video application processing unit of the opponent wireless communication terminal.
6. A wireless communications system according to claim 5, characterized in that communication between audio application processing units is continuously switched to communication between video application processing units by signaling communication between respective client processing units in response to the status change notification from the seamless application processing unit of the wireless communication terminal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An analog-to-digital-converter (ADC), comprising:
a first capacitive digital-to-analog-converter (CDAC), comprising n capacitors corresponding to n bits, the CDAC being configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k\u22121)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k\u22121)th bits that are less significant than the kth bit, wherein k is an integer ranging from 1 to n; and
a control circuit, configured to estimate a weight of the kth bit based on the first and second digital code, the control circuit further configured to perform calibration of the CDAC capacitors based on the estimated weight.
2. The ADC of claim 1, wherein:
the first CDAC is further configured to sample an analog input, and convert the sampled analog input to an n-bit digital output; and
the control circuit is further configured to calibrate the kth bit of the n-bit digital output based on the estimated weight of the kth bit.
3. The ADC of claim 1, wherein the control circuit is further configured to inject a small-signal noise into the first and second analog signals; and
the small-signal noise has a mean substantially equaling 0.
4. The ADC of claim 1, wherein:
the first CDAC further comprises quantization bits, having a resolution less than that of the n bits, configured to estimate a first quantization error of the first analog signal, and estimate a second quantization error of the second analog signal using the quantization bits; and
the control circuit is configured to estimate the weight of the kth bit based on the first and second digital code and the first and second quantization errors.
5. The ADC of claim 1, wherein the kth bit has a first weight that is less than a sum of weights of the 0th through (k\u22121)th bits.
6. The ADC of claim 1, wherein the control circuit is configured to determine a difference of first and second digital code to represent the weight of the kth bit.
7. The ADC of claim 1, further comprises
a bridge capacitor, coupled to the first CDAC; and
a second CDAC, coupled to the bridge capacitor, comprising m bits, wherein an ith bit of the m bits has a second weight that is less than a sum of weights of the 0th through (i\u22121)th bits.
8. An analog-to-digital-converter (ADC), comprising:
a first capacitive digital-to-analog-converter (DAC), comprising n capacitors corresponding to n bits, the CDAC being configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, inject a first small-signal noise into the first analog signals, and convert the injected first analog signal into first digital code using 0th through (k\u22121)th bits that are less significant than the kth bit, wherein k is an integer ranging from 1 to n; and
a control circuit, configured to estimate a weight of the kth bit based on the first digital code, the control circuit further configured to perform calibration of the CDAC capacitors based on the estimated weight.
9. The ADC of claim 8, wherein the small-signal noise has a mean substantially equaling 0.
10. The ADC of claim 8, wherein:
the first CDAC is further configured to connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, inject a second small-signal noise into the second analog signals, and convert the injected second analog signal into second digital code using 0th through (k\u22121)th bits that are less significant than the kth bit; and
the control circuit, configured to estimate the weight of the kth bit based on the first and second digital code.
11. The ADC of claim 8, wherein the control circuit is configured to determine a difference of first and second digital code to represent the weight of the kth bit.
12. The ADC of claim 11, wherein the control circuit is configured to determine a difference of first and second digital code to represent the weight of the kth bit.
13. The ADC of claim 8, wherein:
the first CDAC further comprises quantization bits, having a resolution less than that of the n bits, configured to estimate a first quantization error of the first analog signal, and estimate a second quantization error of the second analog signal using the quantization bits; and
the control circuit is configured to estimate the weight of the kth bit based on the first and second digital code and the first and second quantization errors.
14. The ADC of claim 8, wherein:
the first CDAC is further configured to sample an analog input, and convert the sampled analog input to an n-bit digital output; and
the control circuit is further configured to calibrate the kth bit of the n-bit digital output based on the estimated weight of the kth bit.
15. The ADC of claim 8, wherein the kth bit has a first weight that is less than a sum of weights of the 0th through (k\u22121)th bits.
16. The ADC of claim 8, further comprises
a bridge capacitor, coupled to the first CDAC; and
a second CDAC, coupled to the bridge capacitor, comprising m bits, wherein an ith bit of the m bits has a second weight that is less than a sum of weights of the 0th through (i\u22121)th bits.
17. An analog-to-digital-converter, receiving an analog input signal and outputting digital output data, comprising:
a clock generator, configured to generate a sampling clock with a sampling period and a conversion period;
a sample and hold circuit, configured to sample the analog input signal in a first sampling period to generate a first sampled value, and sample the analog input signal in a subsequent second sampling period to generate a second sampled value;
a storage circuit, configured to hold the first sampled value in the subsequent second sampling period;
a capacitive digital-to-analog-converter (CDAC) and a comparator, configured to convert the first sampled value into first n-bits digital code in a first conversion period, and perform an analog-to-digital conversion to the first sampled value to regenerate a kth bit of n-bits digital code for a plurality of times in a subsequent second sampling period, the CDAC comprising a plurality of capacitors; and
a control circuit configured to determine a kth bit of the digital output data based on the kth bit in the first digital code and the regenerated kth bits, the control circuit being further configured to calibrate the capacitors.
18. The analog-to-digital-converter of claim 17, wherein control circuit is configured to determine a majority of the kth bit in the first digital code and the regenerated kth bits as the kth bit of the digital output data.
19. The analog-to-digital-converter of claim 17, wherein the plurality of times are an even number of times.