1. A high-temperature and high-pressure corrosion-resistant process heat exchanger (60) for a nuclear hydrogen production system, comprising:
at least one second system coolant channel (63a), on one side of which a second system coolant inlet header (61a), into which a high-temperature second system coolant (70), heated by heat from the intermediate heat exchanger (50), is introduced, is provided, in an intermediate portion of which an effective heat transmission region (65), receiving heat from the high-temperature second system coolant (70), is formed, on the other side of which a second system coolant outlet header (61b), out of which a low-temperature second system coolant (71) is discharged, is provided, and which is defined by a quadrilateral corrugated heat transmission fin (65a), which is bent at a predetermined width and height and is disposed in a transverse direction, and by heat transmission plates, which are stacked on upper and lower sides of the heat transmission fin (65b); and
at least one third system coolant channel (63b), which is located on the upper andor lower side of the second system coolant channel (63a), on one side of which a third system coolant inlet header (62a), into which a low-temperature third system coolant (80) is introduced, is provided, in an intermediate portion of which an effective heat transmission region (65), transmitting heat to the low-temperature third system coolant (80), is formed, on the other side of which a third system coolant outlet header (62b), out of which a high-temperature third system coolant (81), heated by reaction with reaction catalysts (90) together with the heat from the effective heat transmission region (65), is discharged, is provided, which is defined by a quadrilateral corrugated heat transmission fin (65a), which is bent at a predetermined width and height and is disposed in a transverse direction, and by heat transmission plates stacked on upper and lower sides of the heat transmission fin (65b), and which includes the reaction catalysts (90) in grooves of the corrugated heat transmission fin (65a).
2. The process heat exchanger according to claim 1, wherein the heat transmission fins (65a) and the heat transmission plates (65b) of the second and third system coolant channels (63a and 63b) are made of a super alloy.
3. The process heat exchanger according to claim 2, wherein, in the third system coolant channel (63b), surfaces of the heat transmission fin (65a) and the heat transmission plate (65b), which come into contact with sulfuric acid (H2SO4) andor sulfite (SO3), are subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance, such as SiC.
4. The process heat exchanger according to claim 3, wherein the heat transmission fin (65a) is bent in a trapezoidal shape.
5. The process heat exchanger according to claim 4, wherein the heat transmission fin (65a) has a horizontal pitch (H) ranging from 3 mm to 8 mm.
6. The process heat exchanger according to claim 4, wherein the heat transmission fin (65a) has a vertical pitch (V) ranging from 3 mm to 8 mm.
7. The process heat exchanger according to claim 1, wherein surfaces of the heat transmission fin (65a) and the heat transmission plate (65b) that come into contact with the high-temperature second system coolant (70), introduced from the second system coolant channel (63a), are subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance.
8. A high-temperature and high-pressure corrosion-resistant process heat exchanger for a nuclear hydrogen production system (1), in which the nuclear hydrogen production system (1) has a first system loop (10) transmitting heat produced from a core (41) of a nuclear reactor (40) to an intermediate heat exchanger (50), a second system loop (20) forcing a second system coolant (70) to be transferred to a process heat exchanger (60) by a second system coolant circulator (23), and a third system loop (30) producing hydrogen using heat transferred from the intermediate heat exchanger (50) to the process heat exchanger (60), the process heat exchanger (60) comprising:
at least one second system coolant channel (63a\u2032), on one side of which a second system coolant inlet header (61a), into which the high-temperature second system coolant (70) heated by the heat from the intermediate heat exchanger (50) is introduced, is provided, in an intermediate portion of which an effective heat transmission region (65), receiving heat from the high-temperature second system coolant (70), is formed, on another side of which a second system coolant outlet header (61b), out of which a low-temperature second system coolant (71) is discharged, is provided, and which is defined by at least one curved channel having a semicircle or semi-ellipse with a predetermined radius (67) in a top surface of a plano-concave heat transmission plate (65b\u2032); and
at least one third system coolant channel (63b), which is located on the upper andor lower side of the second system coolant channel (63a\u2032), on one side of which a third system coolant inlet header (62a), into which a low-temperature third system coolant (80) is introduced, is provided, in an intermediate portion of which an effective heat transmission region (65), transmitting heat to the low-temperature third system coolant (80), is formed, on another side of which a third system coolant outlet header (62b), out of which a high-temperature third system coolant (81) heated by reaction with reaction catalysts (90) together with heat from the effective heat transmission region (65) is discharged, is provided, which is defined by a quadrilateral corrugated heat transmission fin (65a), which is bent at a predetermined width and height and is disposed between the heat transmission plate (65b\u2032) and a flat heat transmission plate (65b) in a transverse direction, and which includes the reaction catalysts (90) in grooves of the corrugated heat transmission fin (65a).
9. The process heat exchanger according to claim 8, wherein the radius (67) of the second system coolant channel (63a) has a range from 0.05 mm to 2.5 mm.
10. The process heat exchanger according to claim 8, wherein the heat transmission fins (65a) and the heat transmission plates (65b and 65b\u2032) of the second and third system coolant channels (63a and 63b) are made of a super alloy.
11. The process heat exchanger according to claim 10, wherein, in the third system coolant channel (63b), surfaces of the heat transmission fin (65a) and the heat transmission plate (65b) that come into contact with sulfuric acid (H2SO4) andor sulfite (SO3) are subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance.
12. The process heat exchanger according to claim 10, wherein, in the third system coolant channel (63b), surfaces of the heat transmission fin (65a) and the heat transmission plate (65b) that come into contact with sulfuric acid (H2SO4) andor sulfite (SO3) are subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance.
13. The process heat exchanger according to claim 10, wherein, in the third system coolant channel (63b), surfaces of the heat transmission fin (65a) and the heat transmission plate (65b) that come into contact with sulfuric acid (H2SO4) andor sulfite (SO3) are subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance.
14. The process heat exchanger according to claim 12, wherein the heat transmission fin (65a) has a vertical pitch V ranging from 3 mm to 8 mm.
15. The process heat exchanger according to claim 8, wherein a surface of the heat transmission plate (65b\u2032) that comes into contact with the high-temperature second system coolant (70), introduced from the second system coolant channel (63a\u2032), is subjected to ion-beam coating and ion-beam mixing using a material having high corrosion resistance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of setting a memory device’s termination impedance in an electrical communication bus having a memory controller connected to a memory device, comprising:
connecting a memory device having a termination device with a corresponding memory controller during training of a drive impedance of a driver of the memory device;
initiating a voltage on the communication bus as a bit level 0 to be read by the memory device;
setting a voltage on a test path of the memory controller at the voltage on the electrical communication bus;
adjusting and monitoring the voltage on the test path; and
when the voltage on the test path switches its value, setting the impedance at the termination device based on said switched voltage.
2. The method of claim 1, wherein the switched voltage on the test path is set as a 0 bit level voltage on the bus.
3. The method of claim 1, wherein said memory device is a GDDR3 memory device.
4. The method of claim 1, wherein a reference voltage for a functional path of the memory controller is set at 0.7 VDD and the 0 bit level voltage on the test path of the memory controller is set at 0.4 VDD, as the switched voltage.
5. The method of claim 1 further comprising:
setting a reference voltage value at a reference resistor arrangement connected to the memory controller at a functional path thereof;
setting an initialized voltage from the electrical communication bus at the test path of the memory controller;
adjusting the voltage at the test path until it changes;
setting the impedance of the termination device based on said changed voltage; and
setting the 0 bit level voltage on the electrical communication bus to correspond to the changed voltage.
6. The method of claim 1, wherein said test path is monitored to detect when said voltage switches said value to a level of 0.4 VDD, and further comprising setting the termination impedance at the termination device based on said voltage level of 0.4 VDD.
7. The method of claim 1, wherein the impedance of the termination device is changed by applying a predetermined current to the memory device based on said changed voltage on said test path.
8. The method of claim 7, wherein said switched voltage is a predetermined value.
9. The method of claim 7, wherein said current is set based on voltage level of 0.4 VDD.
10. The method of claim 7, wherein said memory device is a GDDR3 DRAM.
11. A coupled memory controller and memory device in an electrical communication bus, comprising:
a connection between a memory interface of the memory controller to the memory device, wherein the memory controller is programmed to set a voltage level initialized as a 0 bit level voltage to the memory device, and said memory device having a termination device;
a test path on the memory controller connected to the connection between the memory controller and the memory device to have the initialized voltage level applied thereto, said test path programmed for adjusting said initialized voltage level, and said test path connected to the memory device;
a detector for detecting a predetermined switched voltage on the test path; and
a current module for setting the impedance of the termination device by applying a current to the memory device based on said predetermined switched voltage.
12. The device of claim 11, wherein said detector is programmed for detecting said predetermined switched voltage as 0.4 VDD.
13. The device of claim 11, further comprising said controller being programmed for setting the initialized bit level voltage on the connection between memory controller and the memory device at said switched predetermined level.
14. The device of claim 13, wherein said switched voltage predetermined level is 0.4 VDD.
15. The device of claim 11, wherein said memory device is a GDDR3 DRAM, and said connection between said memory controller and memory device is an electrical communication bus.
16. The device of claim 11, further comprising a current setting device in said memory controller for applying a current to said memory device based on said predetermined switched voltage.
17. The device of claim 16, further comprising a connection from said memory controller to said memory device for applying a current from said current setting device thereto.
18. The device of claim 17, wherein said memory device is a GDDR3 DRAM.
19. The device of claim 18, wherein said initialized voltage is set as a 0 bit level voltage.
20. A coupled memory controller and memory device in an electrical communication bus, comprising:
a connection between a memory interface of the memory controller to the memory device, wherein the memory controller is programmed to set a voltage level initialized as a 0 bit level voltage to the memory device, and said memory device having a termination device;
a test path on the memory controller connected to the connection between the memory controller and the memory device to have the initialized voltage level applied thereto, said test path programmed for adjusting said initialized voltage level, and said test path connected to the memory device;
a detector for detecting a predetermined switched voltage on the test path;
a current module for setting the impedance of the termination device by applying a current to the memory device based on said predetermined switched voltage; and
a current setting device in said memory controller for applying a current to said memory device based on said predetermined switched voltage, and the memory device being a GDDR3 DRAM.