1. A rotationally-molded article having a high-impact polyamide layer comprising a polyamide having a weight average molecular weight of greater than 20,000 gmol and an inherent viscosity of 1.05 dLg or greater, wherein said article has a mean failure energy of at least 100 ft-lbs at \u221220\xb0 C. in an ARM Drop Dart Impact Test, andor an Average Energy at Maximum Load of at least 40 J at \u22122\xb0 C. in ASTM D3763 High Speed Puncture Testing for bi-layer article having a 4 mm thick layer of medium density polyethylene and a 2 mm thick layer of said high impact polyamide; and wherein no plasticizer or mineral oil is added.
2. The rotationally-molded article of claim 1, wherein the molecular weight is in the range of 20,000-35,000 gmol.
3. The rotationally-molded article of claim 1, wherein the inherent viscosity is in the range of from 1.05-1.60 dLg.
4. The rotationally-molded article of claim 1, wherein the molecular weight is in the range of 20,000-30,000 gmol, and the inherent viscosity is in the range of from 1.10-1.40 dLg.
5. The rotationally-molded article of claim 1, wherein said polyamide is selected from the group consisting of PA-6; PA-6,6; PA-6,10; PA-6,12; PA-4,6; PA-11, and PA-12, and blends thereof.
6. The rotationally-molded article of claim 1, further comprising low molecular weight (<20,000 gmol polyamide that is chemically the same or different than the high molecular weight polyamide, wherein said low molecular weight polyamide is blended with the high molecular weight polyamide, and wherein the high molecular weight polyamide represents from 50 to 100 weight percent of the total polyamide.
7. The rotationally-molded article of claim 1, further comprising from 0 to 50 weight percent of one or more impact modifiers, based on the polyamide solids.
8. The rotationally molded article of claim 1, wherein said article has an Average Energy at Maximum Load of at least 20 J at \u221220\xb0 C. in ASTM D3763 High Speed Puncture Testing for a monolayer article consisting of a 3.1 mm thick layer of said high impact polyamide.
9. The rotationally molded article of claim 1, wherein said article is a multi-layer article.
10. The rotationally molded article of claim 1, wherein said high impact polyamide layer is the innermost layer of the article.
11. The rotationally molded article of claim 1, wherein said high impact polyamide layer is the outermost layer of the article.
12. The rotationally molded article of claim 1, wherein said high impact polyamide layer is the intermediate layer of an article consisting of three or more layers.
13. The rotationally molded article of claim 1, wherein said high impact polyamide contains no impact modifier.
14. The rotationally molded article of claim 1, wherein said high impact polyamide contains no plasticizer andor mold release agent.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A PLD, comprising:
at least one PLD circuitry;
at least one IP block; and
a power management circuit configured to control power provided to the at least one PLD circuitry and to the at least one IP block.
2. The PLD according to claim 1, wherein the at least one PLD circuitry comprises programmable logic.
3. The PLD according to claim 1, wherein the at least one PLD circuitry comprises programmable interconnect.
4. The PLD according to claim 1, wherein the at least one PLD circuitry receives power from a first supply.
5. The PLD according to claim 4, wherein the at least one IP block receives power from a second supply.
6. The PLD according to claim 5, wherein the first and second supplies each comprise a regulator integrated within the PLD.
7. The PLD according to claim 1, wherein the power management circuit is further configured to control whether the at least one IP block receives power.
8. The PLD according to claim 1, wherein the power management circuit is further configured to control a level of a power supply voltage.
9. The PLD according to claim 1, wherein the at least one IP block comprises analog circuitry.
10. The PLD according to claim 1, wherein the at least one IP block comprises mixed-signal circuitry.
11. The PLD according to claim 1, wherein the at least one IP block comprises HSSI circuitry.
12. The PLD according to claim 1, wherein the HSSI circuitry comprises a PMA circuit, a PCS circuit, and a MAC circuit.
13. A method of adjusting performance of a PLD, the method comprising:
determining whether the PLD meets a first performance characteristic;
adjusting a body bias level of at least a part of the PLD to a first level according to whether the PLD meets the first performance characteristic;
determining whether the PLD meets a second performance characteristic; and
characterizing the PLD depending on whether the PLD fails to meet the second performance characteristic.
14. The method according to claim 13, further comprising burning at least one fuse in the PLD according to whether the PLD meets the first performance characteristic.
15. The method according to claim 14, wherein burning at least one fuse in the PLD comprises burning the at least one fuse according to the first level.
16. The method according to claim 13, further comprising adjusting the body bias level of at least a part of the PLD to a second level, while monitoring leakage, until a desired performance characteristic is met.
17. The method according to claim 16, further comprising characterizing the PLD and burning at least one fuse in the PLD according to the second level.
18. A method of adjusting performance of a PLD used to implement a user’s design, wherein the PLD comprises a set of IP blocks, the method comprising:
determining whether all IP blocks in the set of IP blocks are used, and selectively disabling provision of power to unused IP blocks;
determining whether the user’s design is to meet performance specifications of a standard; and
controlling a level of power provided to at least one IP block in the set of IP blocks depending on whether the user’s design is to meet performance specifications of the standard.
19. The method according to claim 18, wherein controlling the level of power provided to the at least one IP block in the set of IP blocks comprises providing power so as to meet the performance specifications of the standard, and disabling any unused IP blocks in the set of IP blocks.
20. The method according to claim 18, wherein controlling the level of power provided to the at least one IP block in the set of IP blocks comprises:
determining at least one power level corresponding to the performance specifications of the standard;
providing power so as to meet the performance specifications of the standard; and
disabling any unused IP blocks in the set of IP blocks.
21. A method of adjusting performance of a PLD, the method comprising:
sorting the PLD according to its performance capability;
determining whether any circuit blocks in the PLD inhibit the PLD from meeting desired performance characteristics; and
adjusting a body bias level within the PLD if the any circuit blocks in the PLD inhibit the PLD from meeting the desired performance characteristics.
22. The method according to claim 21, further comprising re-sorting the PLD.
23. The method according to claim 22, further comprising re-adjusting the body bias level.
24. The method according to claim 21, further comprising adjusting a supply voltage provided to a circuit within the PLD.
25. The method according to claim 24, wherein the circuit comprises an IP block.
26. The method according to claim 24, further comprising determining whether the PLD meets the desired performance characteristics.
27. The method according to claim 26, further comprising characterizing a device grade of the PLD.
28. A method of adjusting performance of a PLD during operation of the PLD, the method comprising:
monitoring at least one performance characteristics of the PLD;
determining whether the at least one performance characteristic of the PLD exceeds a desired performance characteristic; and
disabling power to at least one IP block within the PLD if the at least one performance characteristic of the PLD exceeds the desired performance characteristic.
29. The method according to claim 28, further comprising adjusting a supply voltage provided to the ate least one IP block.
30. The method according to claim 28, further comprising adjusting a supply voltage provided to the ate least one IP block rather than disabling power to the at least one IP block if the at least one performance characteristic of the PLD exceeds the desired performance characteristic.
31. The method according to claim 30, wherein the at least one IP block comprises HSSI circuitry.