What is claimed is:
1. A selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between terminals of said gray level reference voltages and an output terminal and each of which has a plurality of serially connected transistors that are drive-controlled in accordance with said input data, each of said select transistor arrays being commonly provided for a group of M (M is a plurality and M<2N) gray level reference voltages among the 2N gray level reference voltages; and
a time division control circuit which causes said select transistor arrays to assume a drive enabled state by means of time division in correspondence with said M gray level reference voltages.
2. The selector circuit as claimed in claim 1, further comprising:
a gray level reference voltage supply circuit which serially supplies, by means of time division, each gray level reference voltage of said group of M gray level reference voltages, to said select transistor array,
wherein said time division control circuit causes said gray level reference voltage supply circuit to serially supply a gray level reference voltage to be driven, among said group of M gray level reference voltages, to said select transistor array; and causes said select transistor arrays to assume a drive enabled state to thereby output the gray level reference voltage to be driven to said output terminal.
3. The selector circuit as claimed in claim 1, further comprising:
a voltage holding circuit for holding voltages supplied to said output terminal,
wherein said time division control circuit causes said select transistor arrays to assume a drive enabled state in correspondence with a gray level reference voltage which is selected in accordance with said input data from among said group of M gray level reference voltages, and then controls the select transistor arrays to be non-conductive and causes said voltage holding circuit to hold the selected gray level reference voltage.
4. The selector circuit as claimed in claim 3, further comprising:
an operational amplifier whose positive input terminal is provided with a voltage held by said voltage holding circuit, the output of the operational amplifier being fed back to the negative input terminal of same.
5. The selector circuit as claimed in claim 3, wherein said select transistor array is constituted by serially connecting a plurality of transistors, to the respective gate of which a partial input data signal of said N bit input data signal is supplied, and a drive control transistor, to the gate of which a drive control signal from said time division control circuit is supplied; and wherein, when said drive control transistor is in a conductive state, said select transistor array assumes a drive enabled state, and, when the drive control transistor is in a non-conductive state, said select transistor array assumes a drive disabled state.
6. The selector circuit as claimed in claim 5,
wherein said M gray level reference voltages include adjacent first and second gray level reference voltages, and
wherein, in a first drive period, said drive control signal causes said drive control transistor to assume a conductive state such that said first gray level reference voltage is outputted to the output terminal via a selected select transistor array, and,
in a second drive period, said drive control signal causes said drive control transistor to assume a conductive state in accordance with the least significant bit of said input data, such that said output terminal changes from said first gray level reference voltage to the second gray level reference voltage via said selected select transistor array.
7. The selector circuit as claimed in claim 3,
wherein said input data signal has first and second data input signals;
said select transistor array is constituted by serially connecting a plurality of transistors, to the respective gate of which said first data signal is supplied, and a drive control transistor, to the gate of which said second data signal is supplied in accordance with a drive control signal from said time division control circuit; and,
when said drive control transistor is in a conductive state, said select transistor array assumes a drive enabled state, and, when the drive control transistor is in a non-conductive state, said select transistor array assumes a drive disabled state.
8. The selector circuit as claimed in claim 7,
wherein said M gray level reference voltages include first and second adjacent gray level reference voltages, and
wherein, in a first drive period, said drive control signal supplies said second data signal to said drive control transistor, such that said first gray level reference voltage is outputted to the output terminal via a selected select transistor array, and,
in a second drive period, said drive control signal supplies said second data signal to said drive control transistor in accordance with the least significant bit of said input data, such that said output terminal changes from said first gray level reference voltage to the second gray level reference voltage via said selected select transistor array.
9. A selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of common reference voltage lines which, by means of time division, are serially supplied with M gray level reference voltages of said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
a voltage holding circuit for holding voltages supplied to said output terminal; and
a time division control circuit which causes said select transistor arrays to assume a drive enabled state in correspondence with a gray level reference voltage which is selected, in accordance with said input data, from among said group of M gray level reference voltages, and then controls the select transistor arrays to be non-conductive and causes said voltage holding circuit to hold the selected gray level reference voltage.
10. The selector circuit as claimed in claim 9, further comprising:
a gray level reference voltage supply circuit for serially supplying, by means of time division, said M gray level reference voltages to said corresponding common reference voltage lines.
11. A selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of common reference voltage lines which, by means of time division, are serially supplied with adjacent first and second gray level reference voltages of said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
a voltage holding circuit for holding voltages supplied to said output terminal; and
a time division control circuit which, in a first drive period, causes said plurality of select transistor arrays to assume a drive enabled state to thereby cause one of said first and second gray level reference voltages to be outputted to said output terminal via a select transistor array selected in accordance with said input data, and, in a second drive period following said first drive period, causes said plurality of select transistor arrays to assume a drive enabled state or a drive disabled state in accordance with a prescribed bit signal of said input data, and, during a drive enabled state, causes the other of the first and second gray level reference voltages to be outputted to said output terminal via said selected select transistor array.
12. The selector circuit as claimed in claim 11,
wherein said 2N gray level reference voltages have first and second gray level reference voltage groups, and
wherein first gray level reference voltages are supplied in said first drive period and second gray level reference voltages are supplied in said second drive period to the common reference voltage lines corresponding to said first gray level reference voltage group, and second gray level reference voltages are supplied in said first drive period and first gray level reference voltages are supplied in said second drive period to the common reference voltage lines corresponding to said second gray level reference voltage group.
13. A liquid crystal display panel driver circuit, comprising:
a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, said selector circuit including:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between terminals of said gray level reference voltages and an output terminal and each of which has a plurality of serially connected transistors that are drive-controlled in accordance with said input data, each of said select transistor arrays being commonly provided for a group of M (M is a plurality and M<2N) gray level reference voltages among the 2N gray level reference voltages; and
a time division control circuit which causes said select transistor arrays to assume a drive enabled state by means of time division in correspondence with said M gray level reference voltages.
14. A liquid crystal display panel driver circuit, comprising:
a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, said selector circuit including:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of common reference voltage lines which, by means of time division, are serially supplied with M gray level reference voltages of said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
a voltage holding circuit for holding voltages supplied to said output terminal; and
a time division control circuit which causes said select transistor arrays to assume a drive enabled state in correspondence with a gray level reference voltage which is selected, in accordance with said input data, from among said group of M gray level reference voltages, and then controls the select transistor arrays to be non-conductive and causes said voltage holding circuit to hold the selected gray level reference voltage.
15. A liquid crystal display panel driver circuit, comprising:
a selector circuit for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprising:
a gray level reference voltage generating section which generates said 2N gray level reference voltages;
a plurality of common reference voltage lines which, by means of time division, are serially supplied with adjacent first and second gray level reference voltages of said 2N gray level reference voltages;
a plurality of select transistor arrays which are provided in parallel between said plurality of common reference voltage lines and an output terminal, and each of which has a plurality of serially connected transistors that are controlled in accordance with said input data;
a voltage holding circuit for holding voltages supplied to said output terminal; and
a time division control circuit which, in a first drive period, causes said plurality of select transistor arrays to assume a drive enabled state to thereby cause one of said first and second gray level reference voltages to be outputted to said output terminal via a select transistor array selected in accordance with said input data, and, in a second drive period following said first drive period, causes said plurality of select transistor arrays to assume a drive enabled state or a drive disabled state in accordance with a prescribed bit signal of said input data, and, during a drive enabled state, causes the other of the first and second gray level reference voltages to be outputted to said output terminal via said selected select transistor array.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for providing an internally generated low noise reference DC voltage in a system that includes at least an analog to digital converter (ADC) circuit connected to a logic circuit, the logic circuit being connected to a pulse width modulator (PWM unit) connected to a filtering circuit arranged to provide the low noise DC reference voltage based upon a PWM output signal, the method comprising:
providing a sensed voltage at an input of the ADC;
converting the sensed voltage to a digital signal;
processing the digital signal by the logic circuit to determine if the sensed voltage is within an acceptable range of voltage values wherein if the sensed voltage is not within the acceptable range, then providing a PWM duty cycle altering feedback signal to the PWM unit; and
altering the DC reference voltage based upon the altered duty cycle PWM output signal; and
updating the sensed voltage based upon the altered DC reference voltage until the sensed voltage is determined to be within the acceptable range of voltage values.
2. The method as recited in claim 1, wherein the filtering circuit is a low pass filter circuit.
3. The method as recited in claim 2, wherein the low pass filter circuit includes a resistor in parallel with a capacitor.
4. The method as recited in claim 1, wherein when the sensed voltage is determined by the logic circuit to be less than a lower voltage threshold value, then the PWM unit responds to the PWM duty cycle altering feedback signal by increasing the PWM duty cycle.
5. The method as recited in claim 1, wherein when the sensed voltage is determined by the logic circuit to be greater than an upper voltage threshold value, then the PWM unit responds to the PWM duty cycle altering feedback signal by decreasing the PWM duty.
6. An apparatus, comprising:
an analog to digital converter (ADC) arranged to convert an analog voltage signal to a corresponding digital signal;
a feedback circuit arranged to receive and process the digital signal;
a pulse width modulation (PWM unit) arranged to provide a modulated signal at a first duty cycle; and
a filtering circuit arranged to provide a reference DC voltage based upon the modulated signal at the first duty cycle, wherein if the analog signal is determined by the feedback circuit to not be within an acceptable range of analog voltage values, then the feedback circuit generates a feedback signal, sends the feedback signal to the to the PWM unit that responds to the feedback signal by altering the duty cycle of the modulated signal, wherein the filtering of the altered duty cycle modulated signal changes the reference DC voltage that in turn updates the analog voltage signal, wherein the feedback continues until the analog signal is determined to be within the range of acceptable voltage values.
7. The apparatus as recited in claim 6, wherein the filtering circuit is a low pass filter circuit.
8. The apparatus as recited in claim 7, wherein the low pass filter circuit includes a resistor in parallel with a capacitor.
9. The apparatus as recited in claim 6, wherein when the analog voltage is determined by the logic circuit to be less than a lower voltage threshold value, then the PWM unit responds to the PWM duty cycle altering feedback signal by increasing the PWM duty cycle.
10. The apparatus as recited in claim 6, wherein when the analog voltage is determined by the logic circuit to be greater than an upper voltage threshold value, then the PWM unit responds to the PWM duty cycle altering feedback signal by decreasing the PWM duty cycle.
11. A light emitting diode (LED) driver circuit, comprising:
an LED having an first node connected to a supply voltage;
an NPN bipolar transistor having a base node at a DC reference voltage, at least one emitter node at an analog voltage related to the DC reference voltage, and a collector node being connected to an second node of the LED;
an analog to digital converter (ADC) having an input node connected to the at least one emitter node, the ADC arranged to convert the analog voltage at the input node to a corresponding digital signal at an ADC output node;
a sense resistor having a first node at the analog voltage connected to the at least one emitter node and a second node connected to ground, wherein a current passing through the LED is substantially equal to a current flowing through the sense resistor biased at the analog voltage;
a logic circuit connected to an output node of the ADC, wherein the logic circuit includes logical elements arranged to process the digital signal;
a pulse width modulator (PWM unit) connected to the logic circuit arranged to generate a modulated digital signal at a first duty cycle at a PWM output node, wherein the logic circuit determines if the analog voltage is within a range of acceptable voltage values by processing the digital signal and generates a PWM duty cycle updating feedback signal when it is determined that the analog voltage is not within the range of acceptable voltage values; and
a filtering circuit connected to the PWM output node arranged to provide the DC reference voltage, wherein the filtering circuit generates the DC reference voltage by filtering the PWM output signal, wherein the PWM unit responds to the duty cycle updating feedback signal by updating the duty cycle of the PWM output signal thereby causing the filtering circuit to update the DC reference voltage that in turn updates the analog voltage until the logic circuit determines that the analog voltage is within the range of acceptable values.
12. The apparatus as recited in claim 11, wherein when the analog voltage is determined by the logic circuit to be less than a lower voltage threshold value, then the PWM unit responds to the PWM duty cycle updating feedback signal by increasing the PWM duty cycle.
13. The apparatus as recited in claim 11, wherein when the analog voltage is determined by the logic circuit to be greater than an upper voltage threshold value, then the PWM unit responds to the PWM duty cycle updating feedback signal by decreasing the PWM duty cycle.
14. A computer readable medium including at least computer program code for providing a low noise reference DC voltage in a system that includes at least an analog to digital converter (ADC) circuit connected to a logic circuit, the logic circuit being connected to a pulse width modulator (PWM unit) connected to a filtering circuit arranged to provide the low noise DC reference voltage based upon a PWM unit output signal, the computer readable medium comprising:
computer program code for providing a sensed voltage at an input of the ADC;
computer program code for converting the sensed voltage to a digital signal;
computer program code for processing the digital signal by the logic circuit to determine if the sensed voltage is within an acceptable range of voltage values wherein if the sensed voltage is not within the acceptable range, then providing a PWM duty cycle altering feedback signal to the PWM unit; and
computer program code for altering the DC reference voltage based upon the altered duty cycle PWM output signal; and
computer program code for updating the sensed voltage based upon the altered DC reference voltage until the sensed voltage is determined to be within the acceptable range of voltage values.
15. The computer readable medium as recited in claim 14, wherein when the analog voltage is determined by the logic circuit to be less than a lower voltage threshold value, then the PWM unit responds to the PWM duty cycle updating feedback signal by increasing the PWM duty cycle.
16. The computer readable medium as recited in claim 14, wherein when the analog voltage is determined by the logic circuit to be greater than an upper voltage threshold value, then the PWM unit responds to the PWM duty cycle updating feedback signal by decreasing the PWM duty cycle.
17. A method of adjusting a current output of a tunable current source, wherein the tunable current source includes an adjustable DC reference voltage generator having an output DC reference voltage adjusted in response to a feedback signal provided by a programmable logic circuit, comprising:
generating the output current by biasing a sense resistor at an analog sense voltage;
converting the analog sense voltage to a digital signal;
digitally processing the digital signal by the programmable logic circuit;
providing the feedback signal to the adjustable DC reference voltage generator only when the processed digital signal indicates that the analog sense voltage is not within a range of acceptable voltage values around a nominal voltage value;
adjusting the nominal voltage value; and
adjusting the output current based upon the adjusted nominal voltage value.
18. The method as recited in claim 17, wherein the nominal voltage value is adjusted during a calibration process.
19. The method as recited in claim 17, wherein the adjustable DC reference voltage generator comprises a pulse width modulation (PWM unit) circuit and a low pass filtering circuit.