1. An integrated circuit comprising a memory cell array comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids,
wherein the memory cell array comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
2. The integrated circuit according to claim 1, wherein at least a part of at least one void is filled with compressible material or material having a negative thermal expansion coefficient.
3. The integrated circuit according to claim 2, wherein the compressible material comprises a nanoporous material.
4. The integrated circuit according to claim 1, wherein the memory cell array comprises a resistive memory cell array.
5. The integrated circuit according to claim 1, wherein the memory cell array comprises a non-volatile memory cell array.
6. The integrated circuit according to claim 1, wherein the memory cell array comprises an active material layer, at least a part of at least one void being located within the active material layer.
7. The integrated circuit according to claim 6, wherein all voids are located within the active material layer.
8. The integrated circuit according to claim 1, wherein all voids are located within at least one dielectric material layer.
9. The integrated circuit according to claim 6, wherein all voids are located within at least one dielectric material layer that is disposed above an active material layer andor an electrode layer that is disposed above the active material layer.
10. The integrated circuit according to claim 2, wherein at least part of at least one void is filled with a material having a negative thermal expansion coefficient, the material comprising a compound.
11. The integrated circuit according to claim 10, wherein the material having a negative thermal expansion coefficient comprises ZrW2O8.
12. An integrated circuit comprising a memory cell array comprising a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient, spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas,
wherein the memory cell array comprises a programmable metallization cell array,
wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
13. The integrated circuit according to claim 12, wherein each stress area comprises a compressible material, the compressible material comprising a nanoporous material.
14. The integrated circuit according to claim 12, wherein the memory cell array comprises a resistive memory cell array.
15. The integrated circuit according to claim 12, wherein the memory cell array comprises a non-volatile memory cell array.
16. The integrated circuit according to claim 12, wherein at least one stress compensation area comprises a trench structure, the trench structure being at least partially filled with the compressible material or the material having a negative thermal expansion coefficient.
17. The integrated circuit according to claim 12, wherein the memory cell array comprises an active material layer, at least a part of at least one stress compensation area being located within the active material layer.
18. The integrated circuit according to claim 17, wherein all stress compensation areas are located within the active material layer.
19. The integrated circuit according to claim 17, wherein all stress compensation areas are located within a dielectric material layer that is disposed above the active material layer.
20. The integrated circuit according to claim 12, wherein the memory cell array comprises a phase changing memory cell array.
21. The integrated circuit according to claim 12, further comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.
22. The integrated circuit according to claim 12, wherein each stress compensation area comprises ZrW.sub.2O.sub.8.
23. A memory cell array comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids,
wherein the memory cell array comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and the at least one dielectric layer that is disposed above the solid electrolyte layer.
24. A memory cell array comprising a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient; and spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas,
wherein the memory cell array comprises a programmable metallization cell array,
wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
25. A memory module comprising at least one memory device comprising a memory cell array that comprises a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids, wherein the memory module comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
26. A memory module comprising at least one memory device comprising a memory cell array that comprises a plurality of mechanical stress compensation areas, each stress compensation area comprising compressible material or material having a negative thermal expansion coefficient; and spatial positions and dimensions of the stress compensation areas being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the stress compensation areas,
wherein the memory module comprises a programmable metallization cell array, wherein the memory cell array comprises a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer that is positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one stress compensation area is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
27. The memory module according to claim 26, wherein the memory module is stackable.
28. A semiconductor device comprising a plurality of voids, spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the device is at least partly compensated by the voids,
wherein the semiconductor device comprises a solid electrolyte random access memory cell array comprising a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer positioned between the reactive electrode layer and the inert electrode layer, the solid electrolyte layer being electrically connected to the reactive electrode layer and the inert electrode layer, and
wherein at least a part of at least one void is located within at least one of the solid electrolyte layer, the inert electrode layer, the reactive electrode layer, and at least one dielectric layer that is disposed above the solid electrolyte layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method comprising:
receiving user data associated with a user’s interaction with Web content;
responsive to receiving the user data, processing the user data to identify sensitive data in the user data;
accessing, from a key manager computing device, a time-limited encryption key;
encrypting the sensitive data with the time-limited encryption key effective to provide encrypted sensitive data; and
providing the encrypted sensitive data to a data consumer.
2. The method of claim 1, wherein the user data is associated with the user’s interaction with an advertisement.
3. The method of claim 1, wherein the user data is associated with the user’s interaction with a search engine.
4. The method of claim 1, wherein the sensitive data comprises one or more of an IP address, location data, a name, or financial data.
5. The method of claim 1 wherein the time-limited encryption key is associated with the data consumer.
6. The method of claim 1, further comprising deleting the time-limited encryption key at a defined time.
7. The method of claim 1, further comprising:
generating a request for the time-limited encryption key;
delivering the request for the time-limited encryption key to the key manager computing device; and
responsive to said delivering, receiving the time-limited encryption key from the key manager computing device.
8. The method of claim 1, further comprising:
identifying an entity identifier associated with the sensitive data effective to define entity specific sensitive data;
generating a request for an entity specific time-limited encryption key according to the entity identifier;
delivering the request for the entity specific time-limited encryption key to the key manager computing device;
receiving the entity specific time-limited encryption key from the key manager computing device;
encrypting the entity specific sensitive data with the entity specific time-limited encryption key effective to produce encrypted entity specific sensitive data; and
providing the data consumer associated with the encrypted entity specific sensitive data with access to the encrypted entity specific sensitive data.
9. The method of claim 1, wherein the time-limited encryption key comprises a time-stamped encryption key.
10. One or more computer-readable storage media comprising instructions that are executable to cause a computing device to perform a process comprising:
receiving user data;
processing the user data to identify one or more entity identifiers associated with one or more respective entities;
identifying entity specific sensitive data within the user data, the entity specific sensitive data being associated with at least one of the entities; and
encrypting the entity specific sensitive data with a time-limited encryption key specifically associated with said at least one of the entities effective to produce encrypted entity specific sensitive data.
11. The one or more computer-readable storage media of claim 10, wherein the process further comprises providing the encrypted entity specific sensitive data to said at least one of the entities.
12. The one or more computer-readable storage media of claim 11, wherein said receiving the user data comprises receiving the user data in association with a user’s online interaction with Web content.
13. The one or more computer-readable storage media of claim 11, wherein the process further comprises deleting the time-limited encryption key.
14. The one or more computer-readable storage media of claim 11, wherein the time-limited encryption key comprises a time-stamped encryption key.
15. The one or more computer-readable storage media of claim 11, wherein said processing the user data identifies multiple entity identifiers associated with multiple respective entities, said identifying entity specific sensitive data comprising identifying entity specific sensitive data associated, respectively, with the multiple respective entities; said encrypting the entity specific sensitive data comprising encrypting entity specific data portions associated with individual entities of the multiple respective entities with respective entity specific time-limited encryption keys each of which being associated with an individual entity; said providing encrypted entity specific sensitive data comprising providing encrypted sensitive data portions to a respective associated entity.
16. The one or more computer-readable storage media of claim 11, wherein the process further comprises:
generating a request for an entity specific time-limited encryption key according to the entity identifier;
delivering the request for the entity specific time-limited encryption key to a key manager computing device;
receiving the entity specific time-limited encryption key from the key manager computing device;
encrypting the entity specific sensitive data with the entity specific time-limited encryption key effective to produce encrypted entity specific sensitive data; and
providing an entity associated with the encrypted entity specific sensitive data with access to the encrypted entity specific sensitive data.
17. The one or more computer-readable storage media of claim 10, wherein the process further comprises:
providing a controlled representation of the entity specific sensitive data to a data consumer, wherein the entity specific sensitive data does not have copy capabilities and becomes inaccessible at a data retention deadline; and
deleting the time-limited encryption key.
18. A system comprising:
one or more processors;
one or more computer readable storage media;
one or more modules embodied on the one or more computer readable storage media and executable under the influence of the one or more processors to:
generate a key generation instruction according to a key generation policy;
responsive to the key generation instruction, generate a time-limited encryption key;
store the time-limited encryption key in a protected database;
generate an encryption key access instruction according to a data access policy; and
responsive to the encryption key access instruction, provide an online service provider with access to the protected database storing the time-limited encryption key.
19. The system of claim 18, wherein the one or more modules are further executable to:
receive a request for the time-limited encryption key from an advertising center; and
responsive to receiving the request for the time-limited encryption key, identify the key generation policy to follow.
20. The system of claim 18, wherein the one or more modules are further executable to:
select a data retention policy with a data retention policy deadline to enforce;
identify a date and time associated with the time-limited encryption key stored in the protected database;
compare the date and time with the data retention policy deadline; and
delete from the protected database the time-limited encryption key at the data retention policy deadline.