1. An antimicrobial pouch comprising:
an antimicrobial agent supporting an antimicrobial substance in a porous inorganic solid carrier;
a first pouch body receiving the antimicrobial agent; and
a second pouch body receiving the first pouch body,
wherein the first pouch body comprises fine holes on an entire surface, the fine holes having a diameter smaller than a particle size of the inorganic solid carrier, and the second pouch body comprises a release hole through which the antimicrobial substance is released to atmosphere.
2. The antimicrobial pouch according to claim 1, wherein the second pouch body is provided with holes used for suspending the second pouch body.
3. The antimicrobial pouch according to claim 1, wherein the second pouch body is manufactured by stacking two sheets of light blocking films and pressure-bonding a periphery of the light blocking films.
4. The antimicrobial pouch according to claim 1, wherein the second pouch body comprises a space in a region where the first pouch body contacts an inside of the second pouch body, and a space between the first pouch body and the second pouch body, and the release hole is provided in a region where the spaces of the second pouch body are formed.
5. The antimicrobial pouch according to claim 1, wherein the release hole is provided at an edge portion of the second pouch body.
6. The antimicrobial pouch according to claim 5, wherein the plurality of release hole are provided, and at least a part of the respective release holes are provided at the edge portion of the second pouch body.
7. The antimicrobial pouch according to claim 1, wherein the second pouch body has a flat polygonal shape.
8. The antimicrobial pouch according to claim 1, wherein a volume ratio of the first pouch body to the second pouch body is 1:3 to 1:1.2.
9. The antimicrobial pouch according claim 1, wherein the inorganic solid carrier is a particle having an average particle size of 0.01 to 1 mm, and a filling rate of the inorganic solid carrier in the first pouch body is 30 to 80%.
10. The antimicrobial pouch according to claim 1, wherein the release hole is blocked by a peelable seal.
11. The antimicrobial pouch according to claim 1, wherein the antimicrobial substance is chlorine dioxide, and the inorganic solid carrier is at least one selected from sepiolite, zeolite, silica, alumina, and silica alumina.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for system integration, said method comprising:
accessing, by a processor from a memory, a chip-level performance specification, a chip-level reliability specification and an inventory,
said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,
said specific system having a system-level reliability specification,
said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and
said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and,
selecting, by said processor from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level performance specification and said chip-level reliability specification.
2. The method of claim 1, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.
3. The method of claim 2, further comprising, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, receiving, by said processor, feedback as to an actual number of power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, by said processor for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).
4. The method of claim 1,
each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and
each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.
5. The method of claim 4, said reliability level indicating a minimum number of power on hours (POHs) during which each manufactured instance of said specific integrated circuit chip contained in said bin is expected, with a specified probability, to perform without fail.
6. The method of claim 1, said inventory associating an identifier with each of said bins, said identifier indicating said specific integrated circuit chip, a specific performance process window and a reliability level.
7. The method of claim 1, said different performance process windows comprising different ranges of maximum oscillation frequency.
8. The method of claim 1, further comprising repeating, by said processor, said accessing and said selecting for each additional integrated circuit chip identified for incorporation into said specific system.
9. A computer system for system integration, said computer system comprising:
a memory storing a chip-level performance specification, a chip-level reliability specification and an inventory,
said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,
said specific system having a system-level reliability specification,
said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and
said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and,
a processor accessing said memory and selecting, from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level reliability specification.
10. The computer system of claim 9, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.
11. The computer system of claim 10, said processor further receiving, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, feedback as to an actual number power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).
12. The computer system of claim 9,
each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and
each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.
13. The computer system of claim 12, said reliability level indicating a minimum number of power on hours (POHs) during which each manufactured instance of said specific integrated circuit chip contained in said bin is expected, with a specified probability, to perform without fail.
14. The computer system of claim 9, said inventory associating an identifier with each of said bins, said identifier indicating said specific integrated circuit chip, a specific performance process window and a reliability level.
15. The computer system of claim 9, said different performance process windows comprising different ranges of maximum oscillation frequency.
16. The computer system of claim 9, said processor further repeating said accessing and said selecting for each additional integrated circuit chip identified for incorporation into said specific system.
17. A computer program product for system integration, said computer program product comprising a computer readable storage medium storing a program instructions, said program instructions being executable by a computer system to cause said computer system to perform a method, said method comprising:
accessing, from a memory, a chip-level performance specification, a chip-level reliability specification and an inventory,
said chip-level performance specification and said chip-level reliability specification each being for a specific integrated circuit chip identified for incorporation into a specific system,
said specific system having a system-level reliability specification,
said chip-level reliability specification being defined so that, when said specific integrated circuit chip is incorporated into said specific system, said specific system meets said system-level reliability specification, and
said inventory referencing manufactured instances of said specific integrated circuit chip sorted into bins associated with different performance process windows and assigned different reliability levels; and,
selecting, from said inventory, one of said manufactured instances of said specific integrated circuit chip from one of said bins for incorporation into said specific system, said one of said manufactured instances of said specific integrated circuit chip being selected to meet said chip-level reliability specification.
18. The computer program product of claim 17, said chip-level reliability specification being defined based on an estimated number of power on hours (POHs) for said specific integrated circuit chip during a useful life of said specific system and comprising a minimum number of power on hours (POHs) during which said specific integrated circuit chip is expected, with a specified probability, to perform without fail.
19. The computer program product of claim 18, said method further comprising, after said one of said manufactured instances of said specific integrated circuit chip is incorporated into said specific system, receiving feedback as to an actual number of power on hours (POHs) of said one of said manufactured instances of said specific integrated circuit chip within said specific system and adjusting, for use during a subsequent integrated circuit chip selection process, said estimated number of power on hours (POHs) based on said actual number of power on hours (POHs).
20. The computer program product of claim 17,
each bin being associated with a specific performance process window and any manufactured instances of said specific integrated circuit chip in said bin exhibiting, during performance testing, performance values within said specific performance process window, and
each bin further being assigned a reliability level, said reliability level being determined using an aggregate reliability model for said any manufactured instances of said specific integrated circuit chip in said bin and said aggregate reliability model being generated based on reliability models associated with different failure mechanisms for said any manufactured instances of said specific integrated circuit chip in said bin.