1. A method of making a semiconductor device to be soldered with an Sn\u2014Ag\u2014Cu type solder to a substrate, the method comprising:
(a) sealing the semiconductor device in a package by surrounding it with thermosetting epoxy resin and thermally curing the resin at a first temperature;
(b) baking the thermosetting epoxy resin at a second temperature not higher than the first temperature;
(c) further baking the thermosetting epoxy resin at a third temperature higher than the first temperature, wherein the third temperature is between about 220\xb0 C. and about 260\xb0 C.; and
(d) inspecting the semiconductor device.
2. A method as in claim 1 wherein step (b) advances curing of the thermo setting epoxy resin.
3. A method as in claim 1 wherein the semiconductor device comprises an integrated circuit.
4. A method as in claim 1 wherein step (a) includes a transfer molding process.
5. A method as in claim 1 wherein step (a) includes a potting process.
6. A method as in claim 1 wherein a conductive lead is adhesively affixed to a main surface of the semiconductor device.
7. A method as in claim 6 wherein the conductive lead is adhesively affixed to a peripheral portion of the main surface of the semiconductor device.
8. A method as in claim 7 wherein an electrode of the semiconductor device is electrically connected to the conductive lead.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package-on-package (POP) electronic device comprising:
first and second packaging substrates;
a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates; and
first and second sealing layers between the first and second packaging substrates; wherein the first sealing layer comprises a mold layer on the first packaging substrate having a via therethrough, wherein the solder interconnection extends through the via, and wherein portions of the second sealing layer are in the via between the mold layer and the solder interconnection.
2. The POP electronic device of claim 1 wherein the first and second sealing layers comprise respective first and second epoxy sealing layers.
3. The POP electronic device of claim 2 wherein the second epoxy sealing layer includes a solder flux agent, and wherein the first epoxy sealing layer has a lower concentration of the solder flux agent than the second epoxy sealing layer.
4. The POP electronic device of claim 1 wherein sidewalls of the via through the mold layer have a surface roughness that is greater than a surface roughness of a surface of the mold layer that is spaced apart from the first packaging substrate.
5. The POP electronic device of claim 1 wherein the first and second sealing layers are spaced apart between the first and second packaging substrates.
6. The POP electronic device of claim 1 further comprising:
a semiconductor integrated circuit (IC) device electrically and mechanically coupled to the first packaging substrate wherein the semiconductor IC device is between the first and second packaging substrates and wherein the semiconductor IC device is spaced apart from the solder interconnection.
7. The POP electronic device of claim 6 wherein the semiconductor IC device comprises a first semiconductor IC device, the POP electronic device further comprising:
a second semiconductor IC device electrically and mechanically coupled to the second packaging substrate wherein the second packaging substrate is between the second semiconductor IC device and the first packaging substrate; a mold layer between the first and second packaging substrates wherein the mold layer includes a via therethrough, wherein the solder interconnection extends through the via between the first and second packaging substrates, and wherein portions of the sealing layer are in the via between the mold layer and the solder interconnection.
8. The POP electronic device of claim 7 further comprising:
a plurality of solder bumps between the second semiconductor IC device and the second packaging substrate wherein the plurality of solder bumps provide electrical and mechanical coupling between the second semiconductor IC device and the second packaging substrate.
9. The POP electronic device of claim 7 further comprising:
a third semiconductor IC device electrically coupled to the second packaging substrate, wherein the third semiconductor IC device is on the second semiconductor IC device with the second semiconductor IC device between the third semiconductor IC device and the second packaging substrate.
10. The POP electronic device of claim 1 wherein the first packaging substrate has first and second surfaces, wherein the first surface is between the second surface and the second packaging substrate, the POP electronic device further comprising:
a plurality of solder bumps on the second surface of the first packaging substrate, wherein an electrical coupling is provided through the first packaging substrate between the solder interconnection and at least one of the plurality of solder bumps.
11. A package-on-package (POP) electronic device comprising:
a first packaging substrate;
a semiconductor integrated circuit (IC) device electrically and mechanically coupled to the first packaging substrate;
a second packaging substrate on the first packaging substrate with the semiconductor IC device between the first and second packaging substrates;
a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates with the solder interconnection being spaced apart from the semiconductor IC device;
a sealing layer on the solder interconnection between the first and second packaging substrates; and
a mold layer between the first and second packaging substrates wherein the mold layer includes a via therethrough, wherein the solder interconnection extends through the via between the first and second packaging substrates, and wherein portions of the sealing layer are in the via between the mold layer and the solder interconnection.
12. The POP electronic device of claim 11 wherein the solder interconnection comprises a first solder interconnection, the device further comprising:
a second solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates with the second solder interconnection being spaced apart from the first solder interconnection and being spaced apart from the semiconductor IC device.
13. The POP electronic device of claim 12 wherein the sealing layer comprises a first sealing layer, the device further comprising:
a second sealing layer on the second solder interconnection between the first and second packaging substrates wherein the first and second sealing layers are spaced apart between the first and second solder interconnection structures.
14. The POP electronic device of claim 12 wherein the sealing layer comprises a continuous sealing layer on the first and second solder interconnection structures between the first and second packaging substrates.
15. The POP electronic device of claim 11 further comprising:
a plurality of solder bumps providing electrical and mechanical coupling between the semiconductor IC device and the first packaging substrate; and
an underfill material on the plurality of solder bumps between the first semiconductor IC device and the first packaging substrate.
16. The POP electronic device of claim 11 wherein portions of the sealing layer are between the mold layer and the second packaging substrate.
17. The POP electronic device of claim 11 wherein a surface of the semiconductor IC device adjacent the second packaging substrate is free of the mold layer.
18. The POP electronic device of claim 11 wherein sidewalls of the via through the mold layer have a surface roughness that is greater than a surface roughness of a surface of the mold layer that is spaced apart from the first packaging substrate.