1. A semiconductor memory device comprising:
a plurality of memory cells each of which includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor which has one end of its current path connected to one end of a current path of the first MOS transistor, the second MOS transistor in a selected one of the memory cells being turned on when data is read from the first MOS transistor in the selected one of the memory cells;
a plurality of local bit lines each of which connects other ends of the current paths of the first MOS transistors;
a global bit line to which two or more of the local bit lines are connected in common;
a first switch element which makes a connection between the local bit lines and the global bit line; and
a latch circuit which is connected to the global bit line and holds data to be written into the memory cells.
2. The semiconductor memory device according to claim 1, further comprising:
word lines each of which connects the control gates of plurality of the memory cells in common.
3. The semiconductor memory device according to claim 1, wherein
the data is written into the memory cells by exchanging electrons with the charge accumulation layer by FN tunneling.
4. The semiconductor memory device according to claim 1, further comprising:
a sense amplifier which amplifies read data, wherein
the global bit line includes a write global bit line and a read global bit line,
the first switch element includes a second switch which makes a connection between the write global bit line and the local bit lines and a third switch element which makes a connection between the read global bit line and the local bit lines,
the latch circuit is connected to the write global bit line, and
the sense amplifier is connected to the read global bit line.
5. The semiconductor memory device according to claim 4, wherein the third switch element includes
a third MOS transistor which has one end of its current path connected to the local bit lines and the other end of its current path, and
a fourth MOS transistor which has one end of its current path connected to the other end of the current path of the third MOS transistor, other end of its current path connected to the read global bit line and a gate insulating film thinner than that of the third MOS transistor.
6. The semiconductor memory device according to claim 4, wherein the potential of the write global bit line is set at the ground potential in a read operation.
7. The semiconductor memory device according to claim 1, further comprising:
a sense amplifier which is connected to one end of the global bit line and amplifies read data; and
a third MOS transistor which has one end of its current path connected to the connection node of the local bit lines and the first switch element and the other end of its current path connected to a first potential, wherein
the latch circuit is connected to the other end of the global bit line, and
the gates of the third MOS transistors connected to the local bit lines sharing the global bit line are independent of one another.
8. The semiconductor memory device according to claim 1, further comprising:
a source line to which the other ends of the current paths of the second MOS transistors in the memory cells are connected in common; and
a source line driver which supplies a potential to the source line.
9. The semiconductor memory device according to claim 1, wherein a negative voltage is applied to the local bit lines in a write operation and a negative voltage is applied to the control gate of the first MOS transistor in an erase operation.
10. The semiconductor memory device according to claim 1, further comprising:
a plurality of cell blocks including two columns of the memory cells connected to two of the local bit lines respectively; and
a sense amplifier which amplifies the data read from the memory cells, wherein
each of the global bit lines includes two write global bit lines and one read global bit line,
the first switch element includes a second and a third switch element, and
in each of the cell blocks, two of the local bit lines are connected to the two write global bit lines via the second switch respectively and are connected to the one read global bit line via the third switch element in common,
the latch circuit is connected to each of the write global bit lines, and the sense amplifier is connected to each of the read global bit lines.
11. The semiconductor memory device according to claim 1, further comprising:
a plurality of cell blocks including four columns of the memory cells connected to four of the local bit lines respectively; and
a sense amplifier which amplifies the data read from the memory cells, wherein
each of the global bit lines includes two write global bit lines and one read global bit line,
the first switch element includes a second and a third switch element, and
in each of the cell blocks, two of the local bit lines are connected in common to one of the write global bit lines via the second switch element, the remaining two local bit lines are connected in common to the other of the write global bit lines via the second switch element, and the read global bit line is connected to all of the four local bit lines via the third switch element,
the latch circuit is connected to each of the write global bit lines, and
the sense amplifier is connected to each of the read global bit lines.
12. The semiconductor memory device according to claim 1, further comprising:
a plurality of cell blocks including two columns of the memory cells connected to two of the local bit lines respectively;
a second switch element which is provided for each of the cell blocks and makes a connection between the two local bit lines and a first potential node; and
a sense amplifier which amplifies the data read from the memory cells, wherein
in each of the cell blocks, two of the local bit lines are connected in common to the global bit line via the first switch and, in a write operation, one of the local bit lines is connected to the global bit line by the first switch and disconnected from the first potential node by the second switch and the other of the local bit lines is connected to the first potential node by the second switch and disconnected from the global bit line by the first switch, and in a read operation, one of the local bit lines is connected to the global bit line by the first switch and the other of the local bit lines is disconnected from the global bit line by the first switch, and
the latch circuit is connected to one end of the global bit line and the sense amplifier is connected to the other end of the global bit line.
13. The semiconductor memory device according to claim 1, further comprising:
a plurality of cell blocks including four columns of the memory cells connected to four of the local bit lines respectively;
a second switch element which is provided for each of the cell blocks and makes a connection between the four local bit lines and a first potential node; and
a sense amplifier which amplifies the data read from the memory cells, wherein
in each of the cell blocks, four of the local bit lines are connected in common to the global bit line via the first switch and, in a write operation, any one of the local bit lines is connected to the global bit line by the first switch and disconnected from the first potential node by the second switch and the remaining three local bit lines are connected to the first potential node by the second switch and disconnected from the global bit line by the first switch, and in a read operation, any one of the local bit lines is connected to the global bit line by the first switch and the remaining three local bit lines are disconnected from the global bit line by the first switch, and
the latch circuit is connected to one end of the global bit line and the sense amplifier is connected to the other end of the global bit line.
14. The semiconductor memory device according to claim 1,
wherein the global bit line is made of a metal wiring layer located at the highest level in a memory cell array which has the memory cells arranged in a matrix.
15. A semiconductor memory device comprising:
a plurality of memory cells each of which includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor which has one end of its current path connected to one end of a current path of the first MOS transistor, the second MOS transistor in a selected one of the memory cell being turned on when data is read from the first MOS transistor in the selected one of the memory cells;
word lines to which the control gates of two or more of the memory cells are connected in common, the data being written into two or more of the memory cells connected to the same word line at the same time by exchanging electrons with the charge accumulation layer by FN tunneling;
a plurality of local bit lines to which the other end of the current path of the first MOS transistor of each of two or more of the memory cells is connected;
a global bit line to which two or more of the local bit lines are connected in common;
a first switch element which makes a connection between the local bit lines and the global bit line; and
a latch circuit which is connected to the global bit line and holds data to be written into the memory cells.
16. The semiconductor memory device according to claim 15, further comprising:
a sense amplifier which amplifies read data, wherein
the global bit line includes a write global bit line and a read global bit line,
the first switch element includes a second switch which makes a connection between the write global bit line and the local bit lines and a third switch element which makes a connection between the read global bit line to the local bit lines,
the latch circuit is connected to the write global bit line, and
the sense amplifier is connected to the read global bit line.
17. The semiconductor memory device according to claim 16,
wherein the third switch element includes a third MOS transistor which has one end of its current path connected to the local bit lines and the other end of its current path, and
a fourth MOS transistor which has one end of its current path connected to the other end of the current path of the third MOS transistor, the other end of the current path connected to the read global bit line and a gate insulating film thinner than that of the third MOS transistor.
18. The semiconductor memory device according to claim 16, wherein the potential of the write global bit line is set at the ground potential in a read operation.
19. The semiconductor memory device according to claim 15, further comprising:
a sense amplifier which is connected to one end of the global bit line and amplifies read data; and
a third MOS transistor has one end of its current path connected to the connection node of the local bit lines and the first switch element and the other end of its current path connected to a first potential, wherein
the latch circuit is connected to the other end of the global bit line, and
the gates of the third MOS transistors connected to the local bit lines sharing the global bit line are independent of one another.
20. The semiconductor memory device according to claim 15, further comprising:
a source line to which the other ends of the current paths of the second MOS transistors in the memory cells are connected in common; and
a source line driver which supplies a potential to the source line.
21. The semiconductor memory device according to claim 15, wherein a negative voltage is applied to the local bit lines in a write operation and a negative voltage is applied to the control gate of the first MOS transistor in an erase operation.
22. The semiconductor memory device according to claim 15, further comprising:
a plurality of cell blocks including two columns of the memory cells connected to two of the local bit lines respectively; and
a sense amplifier which amplifies the data read from the memory cells, wherein
each of the global bit lines includes two write global bit lines and one read global bit line,
the first switch element includes a second and a third switch element, and
in each of the cell blocks, two of the local bit lines are connected to the two write global bit lines via the second switch element respectively, and the read global bit line is connected via the third switch element to the two local bit lines,
the latch circuit is connected to each of the write global bit lines, and
the sense amplifier is connected to each of the read global bit lines.
23. The semiconductor memory device according to claim 15, further comprising:
a plurality of cell blocks including four columns of the memory cells connected to four of the local bit lines respectively; and
a sense amplifier which amplifies the data read from the memory cells, wherein
each of the global bit lines includes two write global bit lines and one read global bit line,
the first switch element includes a second and a third switch element, and
in each of the cell blocks, two of the local bit lines are connected in common to one of the write global bit lines via the second switch element, the remaining two local bit lines are connected in common to the other of the write global bit lines via the second switch element, and the read global bit line is connected to all of the four local bit lines via the third switch element,
the latch circuit is connected to each of the write global bit lines, and
the sense amplifier is connected to each of the read global bit lines.
24. The semiconductor memory device according to claim 15, further comprising:
a plurality of cell blocks including two columns of the memory cells connected to two of the local bit lines respectively;
a second switch element which is provided for each of the cell blocks and makes a connection between the two local bit lines and a first potential node; and
a sense amplifier which amplifies the data read from the memory cells, wherein
in each of the cell blocks, two of the local bit lines are connected in common to the global bit line via the first switch and, in a write operation, one of the local bit lines is connected to the global bit line by the first switch and disconnected from the first potential node by the second switch and the other of the local bit lines is connected to the first potential node by the second switch and disconnected from the global bit line by the first switch, and in a read operation, one of the local bit lines is connected to the global bit line by the first switch and the other of the local bit lines is disconnected from the global bit line by the first switch, and
the latch circuit is connected to one of the global bit line and the sense amplifier is connected to the other end of the global bit line.
25. The semiconductor memory device according to claim 15, further comprising:
a plurality of cell blocks including four columns of the memory cells connected to four of the local bit lines respectively;
a second switch element which is provided for each of the cell blocks and makes a connection between the four local bit lines and a first potential node; and
a sense amplifier which amplifies the data read from the memory cells, wherein
in each of the cell blocks, four of the local bit lines are connected in common to the global bit line via the first switch and, in a write operation, any one of the local bit lines is connected to the global bit line by the first switch and disconnected from the first potential node by the second switch and the remaining three local bit lines are connected to the first potential node by the second switch and disconnected from the global bit line by the first switch, and in a read operation, any one of the local bit lines is connected to the global bit line by the first switch and the remaining three local bit lines are disconnected from the global bit line by the first switch, and
the latch circuit is connected to one of the global bit line and the sense amplifier is connected to the other end of the global bit line.
26. The semiconductor memory device according to claim 15, wherein the global bit line is made of a metal wiring layer located at the highest level in a memory cell array which has the memory cells arranged in a matrix.
27. A semiconductor memory device comprising:
a plurality of memory cells each of which includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor which has one end of its current path connected to one end of a current path of the first MOS transistor, the second MOS transistor in a selected one of the memory cells being turned on when data is read from the first MOS transistor in the selected one of the memory cells;
a plurality of cell blocks in each of which the memory cells are arranged in a matrix;
a memory cell array which has the cell blocks arranged in a matrix;
a plurality of local bit lines to which the other ends of the current paths of the first MOS transistors of the memory cells in the same column are connected in common in each of the cell blocks;
a plurality of global bit lines to which the local bit lines in the same column are connected in common in the memory cell array;
a first switch element which makes a connection between the local bit lines and the global bit lines; and
a latch circuit which is connected to each of the global bit lines and holds data to be written into the memory cells.
28. The semiconductor memory device according to claim 27, further comprising:
word lines to which the control gates of the memory cells in the same row are connected in common.
29. The semiconductor memory device according to claim 27, wherein the data is written into the memory cells by exchanging electrons with the charge accumulation layer by FN tunneling.
30. The semiconductor memory device according to claim 27, further comprising:
a sense amplifier which amplifies read data, wherein
the global bit lines include write global bit lines and read global bit lines,
the first switch element includes a second switch which makes a connection between the write global bit lines and the local bit lines and a third switch element which makes a connection between the read global bit lines and the local bit lines,
the latch circuit is connected to the write global bit lines, and
the sense amplifier is connected to the read global bit lines.
31. The semiconductor memory device according to claim 30, wherein the third switch element includes a third MOS transistor which has one end of its current path connected to the local bit lines and the other end of its current path, and
a fourth MOS transistor which has one end of its current path connected to the other end of the current path of the third MOS transistor, the other end of its current path connected to the read global bit lines and a gate insulating film thinner than that of the third MOS transistor.
32. The semiconductor memory device according to claim 30, wherein the potential of the write global bit line is set at the ground potential in a read operation.
33. The semiconductor memory device according to claim 27, further comprising:
a sense amplifier which is connected to one end of the global bit line and amplifies read data; and
a third MOS transistor has one end of its current path connected to the connection node between the local bit lines and the first switch element and the other end of its current path connected to a first potential, wherein
the latch circuit is connected to the other end of the global bit line, and
the gates of the third MOS transistors connected to the local bit lines sharing the global bit line are independent of one another.
34. The semiconductor memory device according to claim 27, further comprising:
a source line to which the other ends of the current paths of the second MOS transistors in the memory cells are connected in common; and
a source line driver which supplies a potential to the source line.
35. The semiconductor memory device according to claim 27, wherein a negative voltage is applied to the local bit lines in a write operation and a negative voltage is applied to the control gate of the first MOS transistor in an erase operation.
36. The semiconductor memory device according to claim 27, wherein the global bit lines are made of a metal wiring layer located at the highest level in the memory cell array which has the memory cells arranged in a matrix.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A display for holding an object and a card with information relating to the object, the display comprising:
a sheet of generally rigid material having a first panel and a second panel extending from, folded back over, and adjacent to the first panel to form a pocket for receiving the card;
at least one first aperture defined through the first panel and at least one second aperture defined through the second panel and aligned with the first aperture; and
at least one fastener extending through the first aperture and the second aperture and adapted to secure the object to the display.
2. The display of claim 1, wherein the object has at least one aperture defined through it, and wherein the fastener has a front end that extends from the first panel so that the fastener can be extended through the object aperture to support the object in suspension.
3. The display of claim 1, wherein the card has at least one aperture defined through it, and wherein the fastener can be extended through the card aperture to secure the card in the pocket.
4. The display of claim 1, wherein the sheet further comprises a third panel extending from the second panel and adapted for mounting to a shelf.
5. The display of claim 1, wherein the pocket has an open top and a closed bottom.
6. The display of claim 1 in combination with the object and the card of claim 1.
7. A display for mounting to a shelf and for holding an object with at least one aperture and a card with at least one aperture defined through it and with information relating to the object, the display comprising:
a sheet of generally rigid material having a first panel, a second panel extending from, folded back over, and adjacent to the first panel to form a pocket with a closed bottom and an open top for receiving the card in the pocket, and a third panel extending from the second panel and adapted for mounting to the shelf;
at least one first aperture defined through the first panel and at least one second aperture defined through the second panel and aligned with the first aperture; and
at least one fastener extending through the first aperture and the second aperture, the fastener having a front end that extends from the first panel, wherein the fastener can be extended through the object aperture to support the object in suspension and extended through the card aperture to secure the card in the pocket.
8. The display of claim 7, wherein the first panel and the second panel are generally vertical, and the third panel is generally horizontal and has a mounting segment for mounting to a top surface of the shelf and a spacer segment disposed between the second panel and the mounting segment.
9. The display of claim 8, wherein a rear end of the fastener extends from the second panel, and wherein the spacer panel has a length that is the same as or greater than the length of the rear end of the fastener
10. The display of claim 8, wherein the spacer segment is configured to permit the display to be mounted to a shelf with a front edge that is generally vertical or that is angled from vertical.
11. The display of claim 7, wherein the first panel and the second panel are generally vertical, and the third panel has a generally vertical mounting segment for mounting to a front edge of the shelf and a generally horizontal spacer segment extending between the second panel and the mounting segment, wherein a rear end of the fastener extends from the second panel and the spacer panel has a length that is the same as or greater than the length of the rear end of the fastener.
12. The display of claim 7, wherein the first panel has a generally vertical upper segment and a lower segment angled with respect to the first panel upper segment, the second panel has a generally vertical upper segment and a lower segment angled with respect to the second panel upper segment, the third panel is defined at a top of the second panel upper segment and adapted for mounting to a front edge of the shelf, the first aperture is defined through the first panel angled lower segment, and the second aperture is defined through the second panel angled lower segment, wherein the second panel does not need to be spaced from the shelf.
13. The display of claim 7, wherein the first panel and the second panel are angled from vertical, and the third panel has a mounting segment that is generally horizontal for mounting to a top surface of the shelf and a riser segment extending between the second panel and the mounting segment and angled with respect to the mounting segment so that the riser segment and the second panel form an inverted V-shape, wherein a top of the first panel is elevated above the shelf when the display is mounted to the shelf.
14. The display of claim 7 in combination with the object and the card of claim 7.
15. The display of claim 14, wherein the card is folded into a base and a flap with the base inserted into the pocket.
16. The display of claim 14, wherein the object has at least a portion that is unpackaged and exposed where consumers can touch the object.
17. A display for mounting to a shelf and for holding an object and a card with information relating to the object, the display comprising:
a sheet of generally rigid material having a first panel, a second panel extending from, folded back over, and adjacent to the first panel, wherein the first panel includes a first segment, a second segment extending at an angle from the first segment, a third segment extending at an angle from the second segment, and a fourth segment extending at an angle from the third segment, wherein the second panel includes a fifth segment extending at an angle from the fourth segment of the first panel, a sixth segment extending at an angle from the fifth segment, a seventh segment extending at an angle from the sixth segment, and an eighth segment extending at an angle from the seventh segment, wherein the first segment and the eighth segment are parallel, the second segment and the seventh segment are parallel, the third segment and the sixth segment are parallel, and the fourth segment and the fifth segment are parallel, wherein the fourth segment defines a mounting segment adapted for mounting to the shelf, and wherein the first segment and the eighth segment form a pocket for receiving the card; and
a fastener coupled to the sheet for supporting the object.
18. The display of claim 17, wherein the fourth segment and the fifth segment are generally horizontal for mounting to a top surface of the shelf, and wherein the first segment and the eighth segment, the second segment and the seventh segment, and the third segment and the sixth segment are configured in a triangular shape.
19. The display of claim 18, further comprising at least one first aperture defined through the first panel and at least one second aperture defined through the second panel and aligned with the first aperture, wherein the fastener extends through the first aperture and the second aperture to support the object in suspension.
20. The display of claim 19, wherein the card has at least one aperture defined through it, and wherein the fastener can be extended through the card aperture to secure the card in the pocket.
21. The display of claim 18, wherein the fastener extends downwardly from the second segment to support the object in suspension.
22. A method for displaying an object and information relating to the object; the method comprising:
providing a display comprising a sheet of generally rigid material having a first panel and a second panel that form a generally flat pocket for receiving the card and a third panel for mounting to a shelf, aligned first and second apertures defined through the first and the second panels, and a fastener for extending through the first and the second apertures;
providing a card with the information relating to the object marked thereon;
inserting the card into the pocket;
positioning the object adjacent the display first panel;
aligning an aperture in the object with the first and second display apertures;
inserting the fastener through the object aperture and the first and second display apertures to secure and suspend the object from the display.
23. The method of claim 22, further comprising forming the aperture in the object.
24. The method of claim 22, further comprising:
aligning an aperture in the card with the first and second display apertures;
inserting the fastener though the card aperture when the fastener is inserted through the object aperture and the first and second display apertures, wherein the card is secured in the pocket.
25. The method of claim 24, further comprising forming the aperture in the card.
26. The method of claim 22, wherein the object is packaged, and further comprising removing the object from the packaging or removing at least a portion of the packaging to expose at least a portion of the object where consumers can touch the object.