That which is claimed is:
1. A method for the management of interrupts in a microprocessor, said interrupts having a two-fold order of priority, on the one hand a software priority and on the other hand a hardware priority, the microprocessor working in two modes, a first mode during which the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable, a second mode during which the execution of an interrupt routine is interrupted by the arrival of a priority interrupt, the mode of operation of the microprocessor being conditioned by the software priority level of the interrupts,
wherein, at the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor.
2. A method for the management of interrupts according to claim 1, wherein the execution of an interrupt routine in progress is interrupted by the arrival of a new interrupt if the software priority level of this interrupt is higher than that of the interrupt in progress.
3. A method for the management of interrupts according to claim 2 wherein, in order that the microprocessor may function in the first mode, one and the same software priority level is assigned to each interrupt.
4. A method for the management of interrupts according to claim 2 or 3, wherein the software priority level assigned to each interrupt is encoded on n bits and wherein said n bits to be loaded into the state register of the microprocessor are contained in n distinct registers.
5. A method for the management of interrupts according to claim 4, wherein the software priority level is encoded on two bits and wherein the highest software priority level is 11 and the lowest software priority level is 10.
6. A method for the management of interrupts according to claim 1, wherein the execution of an interrupt routine in progress is interrupted by the arrival of a new interrupt if the software priority level of this interrupt is greater than that of the interrupt in progress.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A voltage controlled oscillator (VCO), comprising:
a first voltage controlled current source (VCCS) having a control end and a current end, wherein the control end receives a control voltage;
a first negative resistance circuit (NRC) having a first current path and a second current path, wherein first ends of the first and the second current paths are coupled to the current end of the first VCCS;
a first transformer having a primary side and a secondary side, wherein the primary side of the first transformer is coupled to a second end of the first current path of the first NRC, and the secondary side of the first transformer serves as a first output end of the VCO;
a second transformer having a primary side and a secondary side, wherein the primary side of the second transformer is coupled to a second end of the second current path of the first NRC, and the secondary side of the second transformer serves as a second output end of the VCO;
a first transistor having a first end coupled to the secondary side of the first transformer, and a control end coupled to the primary side of the first transformer; and
a second transistor having a first end coupled to the secondary side of the second transformer, and a control end coupled to the primary side of the second transformer; and
a second VCCS having a control end and a current end, wherein the control end receives a second control voltage; and
a second NRC having a first current path and a second current path, wherein first ends of the first and the second current paths of the second NRC are coupled to the current end of the second VCCS, and second ends of the first and the second current paths of the second NRC are respectively coupled to the primary sides of the first and the second transformers; and
a bias voltage generating unit coupled to the control ends of the first and the second VCCs and configured to provide the control voltage and the second control voltage.
2. The VCO as claimed in claim 1, wherein two ends of the primary side of the first transformer are respectively coupled to the second end of the first current path and a first voltage, two ends of the secondary side of the first transformer are respectively coupled to the first end of the first transistor and the first voltage, two ends of the primary side of the second transformer are respectively coupled to the second end of the second current path and the first voltage, and two ends of the secondary side of the second transformer are respectively coupled to the first end of the second transistor and the first voltage.
3. The VCO as claimed in claim 1, wherein second ends of the first transistor and the second transistor are coupled to a second voltage.
4. The VCO as claimed in claim 3, wherein the first voltage is a system voltage, and the second voltage is a ground voltage.
5. The VCO as claimed in claim 1, wherein the first NRC comprises:
a third transistor having a first end and a second end respectively serving as the first end and the second end of the first current path; and
a fourth transistor having a first end and a second end respectively serving as the first end and the second end of the second current path, wherein the second end and a control end of the fourth transistor are respectively coupled to a control end and the second end of the third transistor.
6. The VCO as claimed in claim 5, wherein the first VCCS comprises a fifth transistor having a first end and a control end respectively serving as the current end and the control end of the first VCCS, and a second end of the fifth transistor is coupled to a second voltage.
7. The VCO as claimed in claim 1, further comprising:
a second VCCS having a control end and a current end, wherein the control end receives a second control voltage, and the current end of the second VCCS is coupled to the current end of the first VCCS; and
a bias voltage generating unit coupled to the control ends of the first and the second VCCSs and configured to provide the control voltage and the second control voltage.
8. The VCO as claimed in claim 1, wherein the bias voltage generating unit comprises:
a first current source;
a sixth transistor having a first end and a second end respectively coupled to the first current source and a first voltage, and a control end of the sixth transistor receiving the control voltage;
a second current source; and
a seventh transistor having a first end and a second end respectively coupled to the second current source and a second voltage, and a control end of the seventh transistor receiving the control voltage.
9. The VCO as claimed in claim 8, wherein the bias voltage generating unit further comprises a voltage divider having two ends respectively coupled to the first ends of the sixth transistor and the seventh transistor.
10. A voltage controlled oscillator (VCO), comprising:
a first voltage controlled current source (VCCS) having a control end and a current end, wherein the control end receives a control voltage;
a negative resistance circuit (NRC) having a first current path and a second current path, wherein first ends of the first and the second current paths are coupled to a second voltage;
a first transformer having a primary side and a secondary side, wherein the primary side of the first transformer is coupled to a second end of the first current path of the NRC, and the secondary side of the first transformer serves as a first output end of the VCO;
a second transformer having a primary side and a secondary side, wherein the primary side of the second transformer is coupled to a second end of the second current path of the NRC, and the secondary side of the second transformer serves as a second output end of the VCO;
a first transistor having a first end coupled to the secondary side of the first transformer, a second end coupled to the current end of the first VCCS, and a control end coupled to the primary side of the first transformer; and
a second transistor having a first end coupled to the secondary side of the second transformer, a second end coupled to the current end of the first VCCS, and a control end coupled to the primary side of the second transformer; and
a second VCCS having a control end and a current end, wherein the control end receives a second control voltage, and the current end of the second VCCS is coupled to the current end of the first VCCS; and
a bias voltage generating unit coupled to the control ends of the first and the second VCCSs and configured to provide the control voltage and the second control voltage.
11. The VCO as claimed in claim 10, wherein two ends of the primary side of the first transformer are respectively coupled to the second end of the first current path and a first voltage, two ends of the secondary side of the first transformer are respectively coupled to the first end of the first transistor and the first voltage, two ends of the primary side of the second transformer are respectively coupled to the second end of the second current path and the first voltage, and two ends of the secondary side of the second transformer are respectively coupled to the first end of the second transistor and the first voltage.
12. The VCO as claimed in claim 11, wherein the first voltage is a system voltage, and the second voltage is a ground voltage.
13. The VCO as claimed in claim 10, further comprising a constant current source, wherein the constant current source is coupled between the first ends of the first and the second current paths and the second voltage.
14. The VCO as claimed in claim 10, wherein the first NRC comprises:
a third transistor having a first end and a second end respectively serving as the first end and the second end of the first current path; and
a fourth transistor having a first end and a second end respectively serving as the first end and the second end of the second current path, wherein the second end and a control end of the fourth transistor are respectively coupled to a control end and the second end of the third transistor.
15. The VCO as claimed in claim 14, wherein the first VCCS comprises a fifth transistor having a first end and a control end respectively serving as the current end and the control end of the first VCCS, and a second end of the fifth transistor is coupled to the second voltage.
16. The VCO as claimed in claim 10, wherein the bias voltage generating unit comprises:
a first current source;
a sixth transistor having a first end and a second end respectively coupled to the first current source and a first voltage, and a control end of the sixth transistor receiving a control signal;
a second current source; and
a seventh transistor having a first end and a second end respectively coupled to the second current source and a second voltage, and a control end of the seventh transistor receiving the control signal.
17. The VCO as claimed in claim 16, wherein the bias voltage generating unit further comprises a voltage divider having two ends respectively coupled to the first ends of the sixth transistor and the seventh transistor.