1. A method for forming a non-silicon metalloid-oxane and metallo-oxane, or mixed poly(siliconmetallo)oxane polymer networks, or their hydrido, organic, or organometallic derivatives, comprising condensing an alkoxide substrate with another alkoxide material at neutral or near neutral pH using a catalyst comprising a molecule having a nucleophilic group that displaces alkanol from said alkoxide substrate facilitating solvolysis to initiate structure-directed condensation with said another alkoxide, wherein either or both of said alkoxides is selected from the group consisting of organosilicon alkoxides; hydrido-siicon alkoxides; metallo alkoxides; organometallo-alkoxides; hydrido metallo-alkoxides; metalloid alkoxides; organometalloid alkoxides; and hydrido metalloid alkoxides.
2. The method of claim 1 wherein said structure-directed condensation is by nucleophilic attack.
3. The method of claim 1 wherein said nucleophilic group forms a transitory intermediate in facilitating solvolysis.
4. The method of claim 3 wherein said transitory intermediate is covalent.
5. The method of claim 1 comprising using a group that interacts with said nucleophilic group to increase its nucleophilicity.
6. The method of claim 5 wherein said interaction is by hydrogen bonding.
7. A method for forming a non-silicon metalloid-oxanes, metallo-oxanes, or mixed poly(siliconmetallo)oxane polymer networks, or their hydrido, organic, or organometallic derivatives, comprising condensing a first material with a second material at neutral or near neutral pH using a catalyst comprising a molecule having a nucleophilic group that initiates solvolysis of said first material to promote structure-directed condensation with said second material, wherein either or both of said first or second material is selected from the group consisting of
non-silicon metalloid alkoxides, and metal alkoxides;
inorganic and organic oxygen-containing chelates of silicon, non-silicon metalloids or metals;
inorganic and organic esters, hydrolyzable salts, complexes or conjugates of the hydroxides of silicon, non-silicon metalloids or metals;
and any organic, organometallic and hydrido derivatives of the foregoing.
8. The method of claim 7 wherein one of said first or second material is an organosilicon alkoxide.
9. The method of claim 8 wherein said organosilicon alkoxide is methyl-, phenyl-, or dansylpropyl-triethoxysilane.
10. The method of claim 7 wherein one of said first or second material is a hydrido-silicon alkoxide.
11. The method of claim 10 wherein said hydrido-silicon alkoxide is hydridotriethoxysilane.
12. The method of claim 7 wherein one of said first or second material is a non-silicon metallo alkoxide.
13. The method of claim 12 wherein said non-silicon metallo alkoxide is bis(lactato) titanium.
14. The method of claim 1 wherein either or both of said alkoxides is an organometallo-alkoxide.
15. The method of claim 14 wherein said organometallo-alkoxide is phenyl-bis(lactato) titanium.
16. The method of claim 7 wherein one of said first or second material is a non-silicon hydrido metallo-alkoxide.
17. The method of claim 16 wherein said non-silicon hydrido metallo-alkoxide is hydridobis(lactato) titanium.
18. The method of claim 7 wherein one of said first or second material is a non-silicon metalloid alkoxide.
19. The method of claim 18 wherein said non-silicon metalloid alkoxide is tetraorthoethoxygermanate.
20. The method of claim 7 wherein one of said first or second material is a non-silicon organometalloid alkoxide.
21. The method of claim 20 wherein said non-silicon organometalloid alkoxide is methyl-, phenyl-, or dansylpropyl-tricthoxygermane.
22. The method of claim 7 wherein one of said first or second material is a non-silicon hydrido metalloid alkoxide.
23. The method of claim 22 wherein said non-silicon hydrido metalloid alkoxide is hydrido-triethoxygermane.
24. The method of claim 7 wherein there is formed as a product the corresponding non-silicon metalloid-oxane, metallo-oxane, or mixed poly(siliconmetallo)oxane, polymer networks, or their hydrido, organic, or organometallic derivatives.
25. The method of claim 1 wherein said catalyst molecule is selected from proteins, enzymes, peptides, non-peptide-based polymers, small molecules, supramolecular aggregates, filaments, or arrays or assemblies thereof.
26. The method of claim 25 wherein said catalyst molecule is a protein.
27. The method of claim 25 wherein said catalyst molecule is an enzyme.
28. The method of claim 27 wherein said enzyme is a silicatein.
29. The method of claim 27 wherein said enzyme is a protease.
30. The method of claim 27 wherein said enzyme is a peptidase.
31. The method of claim 27 wherein said enzyme is a hydrolase.
32. The method of claim 31 wherein said hydrolase is selected from the group consisting of amidase, esterase and lipase.
33. The method of claim 27 wherein said enzyme is a catalytic triad enzyme.
34. The method of claim 1 wherein said catalyst molecule is a peptide.
35. The method of claim 34 wherein said peptide contains lysine or poly lysine.
36. The method of claim 34 wherein said peptide contains serine or polyserine.
37. The method of claim 34 wherein said peptide contains a tyrosine.
38. The method of claim 34 wherein said peptide contains a histidine.
39. The method of claim 34 wherein said peptide contains cysteine, oligocysteine or poly-cysteine.
40. The method of claim 34 wherein said peptide contains a nucleophilic catalytic side-chain.
41. The method of claim 40 wherein said nucleophilic catalytic side-chain is contributed by serine, cysteine, histidine or tyrosine.
42. The method of claim 34 wherein said peptide contains a hydrogen-bonding amine.
43. The method of claim 1 wherein said catalyst molecule is a non-peptidebased polymer that operates by a mechanism of catalysis similar to that utilized by silicateins.
44. The method of claim 43 wherein said non-peptide-based polymer contains a hydrogen-bonding amine andor a nucleophilic group.
45. The method of claim 24 wherein said product is a silsesquioxane.
46. The method of claim 24 wherein said product is a polyorganosiloxane.
47. The method of claim 24 wherein said product is a polymetallo-oxane.
48. The method of claim 24 wherein said product is a polyorganometallooxane.
49. The method of claim 24 wherein said product is a polyorganometalloidoxane.
50. The method of claim 1 in which said catalyst molecule is self-assembling whereby said structure-directed condensation is provided by a spatial array of structure-directing determinants contained on or within the self-assembling catalyst molecule.
51. The method of claim 50 in which said spatial array of structure-directing determinants acts in conjunction with the surfaces of any solid support to which said catalyst molecule is attached or in which said catalyst molecule is confined.
52. The method of claim 50 wherein said catalyst molecule is selected from the group consisting of silicatein, protein, enzyme, peptide, and non-peptide-based polymers, andor any aggregate, filament, or other assembly thereof.
53. The method of claim 1 in which said nucleophilic group is provided by a hydroxyl or sulfhydryl group.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for a low power AES (advanced encryption standard) cryptographic circuit for an embedded system, the apparatus comprising:
an interface circuit for inputting and outputting data and a control command in cooperation with a general purpose processor;
a code processing unit for performing a round operation in an operation order of an add round key operation, a sub byte key operation, a shift row operation, and a mix column operation;
a data memory for storing data input through the interface circuit and operation results processed at the code processing unit;
a data selecting unit for selecting data inputoutput to and from the code processing unit and a storing unit; and
a control unit for controlling the code processing unit, the storing unit, and the data selecting unit such that a round operation of a set round is repeatedly performed on data input from the interface circuit, and an add round key operation is performed on a shift row-operated result value and a secret key during a last round.
2. The apparatus of claim 1, wherein the code processing unit performs the round operation on data by a byte unit.
3. The apparatus of claim 1, wherein the code processing unit comprises:
an add round key circuit for performing an add round key operation on one of input data stored in the data memory and operation results of a previous round;
an S-box for performing a sub byte operation on operation results of the add round key circuit;
a shift row circuit for performing a shift row operation on operation results of the S-box; and
a mix column circuit for performing an mix column operation on operation results of the shift row circuit.
4. The apparatus of claim 3, further comprising:
a key memory for storing a secret key input from the interface circuit and a round key generated from the secret key, and providing key data required for an operation of the add round key circuit; and
a round key generating circuit for reading key data stored in the key memory to generate a round key used for each round operation of the code processing unit.
5. The apparatus of claim 4, wherein the round key generating circuit generates a round key of a next round using the S-box when a mix column operation is performed at the code processing unit.
6. The apparatus of claim 4, further comprising a register for temporarily storing one of intermediate results of the code processing unit and intermediate results of the round key generating circuit before storing it in one of the data memory and the key memory.
7. The apparatus of claim 6, wherein the shift row circuit is realized by generating a location movement when operation results of the S-box are stored in the register.
8. The apparatus of claim 7, wherein the S-box is realized as a combination circuit.
9. The apparatus of claim 8, wherein the mix column circuit is realized as a 32-bit shift register and a plurality of 8-bit XOR circuits.
10. The apparatus of claim 9, wherein the add round key circuit is realized as a first XOR operator performing an XOR-operation on outputs of the data memory and the key memory.
11. The apparatus of claim 10, wherein the round key generating circuit comprises:
a constant generator for generating a constant required for generating a round key defined in an AES cryptographic algorithm;
a second XOR operator for performing an XOR-operation on a result value of the S-box and a constant generated at the constant generator; and
a third XOR operator for performing an XOR operation on an operation result of the second XOR operator and a next output value of the key memory.
12. The apparatus of claim 11, wherein the data selecting unit comprises:
a first data selector for selecting one of input data input from the interface circuit, a result of the add round key operation, a result of the shift row operation, and a result of the mix column operation, to store the selected data in the data memory;
a second data selector for selecting one of key data input from the interface circuit and an operation result of the third XOR operator, to store the selected data in the key memory;
a third data selector for selecting one of a result of the add round key operation and an output value of the key memory, to apply the selected data to the S-box;
a fourth data selector for selecting one of an operation result of the S-box and an operation result of the second XOR operator to store the selected data in a register; and
a fifth data selector for selecting one of an operation result of the S-box and an output of the register to provide the selected data as a result of the shift row operation to the first data selector.
13. A method for a low power AES cryptographic circuit for an embedded system, the method comprising:
performing operations on data to be encrypted in an order of an add round key operation, a sub byte operation, a shift row operation, and a mix column operation;
performing operations on a result of a mix column operation of a previous round in an order of the add round key operation, the sub byte operation, and the shift row operation;
after the performing of the operations on the result of the mix column operation, checking whether a current round is a last round;
when the current round is not the last round as a result of the checking, performing operations again starting from the performing of the operations on the result of the mix column operation, after performing a mix column operation on a result of the performing of the operations on the result of the mix column operation;
when the current round is the last round as a result of the checking, performing an add round key operation that uses a secret key on a result of the performing of the operations on the result of the mix column operation; and
outputting, as encryption data, a result value of the performing of the add round key operation that uses the secret key.
14. The method of claim 13, wherein all of the add round key operation, the sub byte operation, and the shift row operation are performed during one clock cycle.
15. The method of claim 13, wherein the add round key operation, the sub byte operation, the shift row operation, and the mix column operation are performed on data by a byte unit.
16. The method of claim 15, wherein the mix column operation stores data by a 8-bit unit using a 32-bit shift register and an 8-bit XOR circuit, and moves to perform an operation at an 8 clock.