1. A substrate comprising an electron donating surface with metal particles on said surface, wherein said metal particles comprise palladium and at least one metal selected from the group consisting of gold, ruthenium, rhodium, osmium, iridium, and platinum and wherein the amount of said metal particles on said surface is from about 0.001 to about 8 \u03bcgcm2.
2. The substrate according to claim 1, wherein said electron donating surface is a layer of an electron donating material at an amount of about 0.05 to about 12 \u03bcgcm2.
3. The substrate according to claim 2, wherein said electron donating layer is a metal that is less noble than any of the metals in the group consisting of palladium, gold, ruthenium, rhodium, osmium, iridium, and platinum.
4. The substrate according to claim 2, wherein said electron donating layer is a metal selected from the group consisting of silver, copper and zinc.
5. The substrate according to claim 1, wherein said substrate is a polymeric substrate.
6. The substrate according to claim 1, wherein said substrate is selected from the group consisting of latex, polymers comprising vinyl groups, silicone, polyvinylchloride, polypropylene, polyurethane, polyester, copolymerisates of ethylene vinyl acetate, polystyrene, polycarbonate, polyethylene, polyacrylate, polymethacrylate, acrylonitrile butadiene styrene, polyamide, and polyimide, or mixtures thereof.
7. The substrate according to claim 1, wherein said substrate is selected from the group consisting of a natural polymer, a degradable polymer, an edible polymer, a biodegradable polymer, an environmental friendly polymer, and a medical grade polymer.
8. The substrate according to claim 1, wherein said substrate is a metal.
9. The substrate according to claim 1, wherein said substrate is selected from the group consisting of stainless steel, medical grade steel, titanium, medical grade titanium, cobalt, and chromium or mixtures thereof.
10. The substrate according to claim 1, wherein said substrate is selected from the group consisting of glass, minerals, zeolites, stone and ceramics.
11. The substrate according to claim 1, wherein said substrate is selected from the group consisting of paper, wood, woven fibres, fibres, cellulose fibres, leather, carbon, carbon fibres, graphite, polytetrafluoroethylene, and polyparaphenyleneterephthalamide.
12. The substrate according to claim 1, wherein said substrate has the shape of a particle.
13. The substrate according to claim 1 wherein the amount of the metal particles on the electron donating surface is from about 0.01 to about 4 \u03bcgcm2.
14. The substrate according to claim 2, wherein the ratio of palladium to non-palladium metals in said metal particles is from about 0.01:99.99 to about 99.99:0.01.
15. The substrate according to claim 2, wherein the ratio of palladium to non-palladium metals in said metal particles is from about 0.5:99.5 to about 99.8:0.2.
16. The substrate according to claim 2, wherein the ratio of palladium to non-palladium metals in said metal particles is from about 2:98 to about 95:5.
17. The substrate according to claim 1 wherein said metal particles, further comprise gold in addition to palladium.
18. The substrate according to claim 1, wherein said metal particles on the electron donating surface have an average size of about 10 to about 10000 \u212b.
19. The substrate according to claim 1, wherein said metal particles on the electron donating surface have an average size of about 100 to about 600 \u212b.
20. An object comprising a substrate according to claim 1.
21. The object according to claim 20, wherein said object is a medical device.
22. The object according to claim 20, wherein said object is a disposable article.
23. The object according to claim 20, wherein said object is a dental article.
24. A method of modifying protein adsorption to an object comprising, applying the substrate of claim 1 to the object.
25. A method of modifying tissue ingrowth on an object comprising, applying the substrate of claim 1 to the object.
26. A method of modifying the complement activation caused by an object comprising, applying the substrate of claim 1 to the object.
27. A method of modifying the inflammatory response caused by an object comprising, applying the substrate of claim 1 to the object.
28. A method of modifying the blood clotting caused by an object comprising, applying the substrate of claim 1 to the object.
29. A method of modifying the friction coefficient of an object comprising, applying the substrate of claim 1 to the object.
30. A method of modifying the surface hardness of an object comprising, applying the substrate of claim 1 to the object.
31. A method for the manufacture of a substrate according to claim 1 comprising the steps:
a. depositing metal particles from a suspension onto said substrate,
b. rinsing said substrate, and
c. drying said substrate.
32. A method according to claim 31 further comprising the step of depositing an electron donating material on said substrate before the step a.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for using a current-steering N-bit DA converter comprising N binary weighted current sources SIk, k0, 1, . . . , N1, connectable to a common output, each current source SIk comprising 2k unit current sources, SIunit, of equal strength connected in parallel, wherein digital input bits bi, i0, 1, . . . , N1, bN1 being the most significant bit (MSB), determine which respective current source, SIk, k0, 1, . . . , N1, to be connected to the output, the method comprising the step of:
during DA conversion substituting the current IN1 from the largest current source SIN1 for a current N1, where
11
I
~
N
–
1
=
(
k
=
0
N
–
2
I
k
)
+
I
unit
in which expression Ik being the current from the current source SIk, and Iunit being the current from an additional unit current source.
2. The method as claimed in claim 1 comprising calibrating the DA converter prior to DA conversion, said calibrating comprising the steps of:
measuring the currents IN1 and N1; and
constructing the current difference I between the measured currents, wherein
the step of substituting comprises forming the current N1, by subtracting the current difference I from the current IN1 of the largest current source.
3. The method as claimed in claim 2 wherein the current difference I is constructed by means of a current mirror.
4. The method as claimed in claim 2 wherein the current difference I is stored in a current memory.
5. The method as claimed in claim 4 wherein the current difference I is stored by charging a capacitor.
6. The method as claimed in claim 2 wherein the calibration is repeated after a predetermined amount of time.
7. The method as claimed in claim 1 wherein the current sources are integrated MOS transistors.
8. A method for using a current-steering N-bit DA converter comprising N binary weighted current sources SIk, k0, 1, . . . , N1, connectable to a common output, each current source SIk comprising 2k unit current sources, Sunit, of equal strength connected in parallel, wherein digital input bits bi, i0, 1, . . . , N1, bN1 being the most significant bit (MSB), determine which respective current source, SIk, k0, 1, . . . , N1, to be connected to the output, the method comprising the step of:
during DA conversion substituting the currents IN1, IN2, . . . , INc, from the c largest current sources SIN1, SIN2, . . . , SINc, c being a positive integer larger than 1, for currents N1, N2, . . . , Nc, where
12
I
~
N
–
1
=
(
k
=
0
N
–
c
–
1
I
k
)
+
(
j
=
N
–
c
N
–
2
I
~
j
)
+
I
unit
I
~
N
–
2
=
(
k
=
0
N
–
c
–
1
I
k
)
+
(
j
=
N
–
c
N
–
3
I
~
j
)
+
I
unit
I
~
N
–
c
=
(
k
=
0
N
–
c
–
1
I
k
)
+
I
unit
in which expressions Ik being the current from the current source SIk, and Iunit being the current from an additional unit current source.
9. The method as claimed in claim 8 comprising calibrating the DA converter prior to DA conversion, said calibrating comprising the steps of:
measuring the currents IN1, IN2, . . . , INc, and N1, N2, . . . , Nc; and
constructing current differences IN1N1, I N2IN2N2, . . . , INcINcNc wherein
the step of substituting comprises forming the respective current N1, N2, . . . , Nc, by subtracting the respective current difference IN1, IN2, . . . , INc from the respective current IN1, IN2, . . . , INc.
10. The method as claimed in claim 8 comprising calibrating the DA converter prior to DA conversion, said calibrating comprising the steps of:
measuring the currents IN1, IN2, . . . , INc, and N1;
constructing a current difference IN1IN1N1; and
providing current differences IN2IN2N2, . . . , INcINcNc, as fractions of IN1, wherein
the step of substituting comprises forming the respective current N1, N2, . . . , Nc, by subtracting the respective current difference IN1, IN2, . . . , INc, from the respective current IN1, IN2, . . . , INc.
11. The method as claimed in claim 10 wherein the fractions are provided by means of prior knowledge of the relative mismatch between the N binary weighted current sources of the DA converter.
12. The method as claimed in claim 9 wherein the current difference IN1 is constructed by means of a current mirror.
13. The method as claimed in claim 9 wherein the current differences IN1, IN2, . . . , INc are stored in a current memory.
14. The method as claimed in claim 13 wherein the current difference IN1 is stored by charging a capacitor.
15. The method as claimed in claim 14 wherein the current differences IN1, IN2, . . . , INc, are restored for the forming of the respective current N1, N2, . . . , Nc, by means of the capacitor controlling transistors connected in parallel.
16. The method as claimed in claim 15 wherein the transistors are NMOS transistors in dependence on the current differences IN1, IN2, . . . , INc being positive.
17. The method as claimed in claim 15 wherein the transistors are PMOS transistors in dependence on the current differences IN1, IN2, . . . , INc being negative.
18. The method as claimed in claim 10 wherein the calibration is repeated after a predetermined amount of time.
19. The method as claimed in claims 10 wherein the current sources are integrated MOS transistors.
20. A current-steering N-bit DA converter comprising:
N digital inputs, each receiving a digital input bit bi, i0, 1, . . . , N1, bN1 being the most significant bit (MSB);
an analog output; and
N binary weighted current sources SIk, k0, 1, . . . , N1, connectable to said analog output, each current source SIkcomprising 2k unit current sources, SIunit, of equal strength connected in parallel, wherein
the digital input bits are indicative of which respective current source, SIk, k0, 1, . . . , N1, to be connected to the analog output, the DA converter further comprising
an additional unit current source and means for substituting the current IN1 from the largest current source SIN1 for a current N1, where
13
I
~
N
–
1
=
(
k
=
0
N
–
2
I
k
)
+
I
unit
in which expression Ik being the current from the current source SIk, and Iunit being the current from said additional unit current source.
21. The DA converter as claimed in claim 20 comprising calibration means for calibrating the DA, said calibration means comprising:
means for measuring the currents IN1 and N1; and
means for constructing the current difference I between the measured currents, wherein
the DA converter comprises means for, during DA conversion, forming the current N1 by subtracting the current difference I from the current IN1 of the largest current source.
22. The DA converter as claimed in claim 21 wherein the means for constructing comprises a current mirror.
23. The DA converter as claimed in claim 21 wherein the current difference I is held in a current memory, particularly comprising a capacitor.
24. The DA converter as claimed in claim 20 wherein the current sources are integrated MOS transistors.
25. A current-steering N-bit DA converter comprising:
N digital inputs, each receiving a digital input bit bi, i0, 1, . . . , N1, bN1 being the most significant bit (MSB);
an analog output; and
N binary weighted current sources SIk, k0, 1, . . . , N1, connectable to said analog output, each current source SIk comprising 2k unit current sources, SIunit, of equal strength connected in parallel, wherein the digital input bits are indicative of which respective current source, SIk, k0, 1, . . . , N1, to be connected to the analog output, the DA converter further comprising
an additional unit current source and means for substituting the currents IN1, IN2, . . . , INc, from the c largest current sources SIN1, SIN2, . . . , SINc, c being a positive integer larger than 1, for currents N1, N2, . . . , Nc,
14
I
~
N
–
1
=
(
k
=
0
N
–
c
–
1
I
k
)
+
(
j
=
N
–
c
N
–
2
I
~
j
)
+
I
unit
I
~
N
–
2
=
(
k
=
0
N
–
c
–
1
I
k
)
+
(
j
=
N
–
c
N
–
3
I
~
j
)
+
I
unit
I
~
N
–
c
=
(
k
=
0
N
–
c
–
1
I
k
)
+
I
unit
in which expressions Ik being the current from the current source SIk, and Iunit being the current from said additional unit current source.
26. The DA converter as claimed in claim 25 comprising means for calibrating the DA converter, said calibrating means comprising:
means for measuring the currents IN1, IN2, . . . , Inc, and N1, N2, . . . , Nc; and
means for constructing current differences, IN2IN2N2, . . . , INcNc wherein
the means for substituting comprises means for forming the respective current N1, N2, . . . , Nc, by subtracting the respective current difference IN1, IN2, . . . , INc from the respective current IN1, IN2, . . . , INc.
27. The DA converter as claimed in claim 25 comprising means for calibrating the DA converter, said calibrating means comprising: means for measuring the currents IN1, IN2, . . . , INc, and N1;
means for constructing current difference IN1IN1N1; and
means for providing current differences IN2IN2N2, . . . , INcINcNc, as fractions of IN1, wherein
the means for substituting comprises means for forming the respective current N1, N2, . . . , Nc, by subtracting the respective current difference IN1, IN2, . . . , INc, from the respective current IN1, IN2, . . . , Inc.
28. The DA converter as claimed in claim 27 wherein the means for providing the fractions are constructed by means of prior knowledge of the relative mismatch between the N binary weighted current sources.
29. The DA converter as claimed in claim 26 wherein the means for constructing comprises a current mirror.
30. The DA converter as claimed in claim 26 wherein the means for forming comprises a capacitor and transistors connected in parallel.
31. The DA converter as claimed in claim 30 wherein the transistors comprise NMOS transistors.
32. The DA converter as claimed in claim 30 wherein the transistors comprise PMOS transistors.
33. The DA converter as claimed in claim 25 wherein the current sources are integrated MOS transistors.