1. A multi-level sensing apparatus of a non-volatile memory, the multi-level sensing apparatus comprising:
a first sense amplifier configured to compare a first reference voltage with a read data of a bit line and amplify a comparison result to generate a first output;
a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output;
a second sense amplifier configured to compare the fourth reference voltage with the read data of the bit line and amplify a comparison result to generate a second output; and
a decoder configured to decode the first and second outputs to output a sensing data.
2. The multi-level sensing apparatus of claim 1, wherein the first and second sense amplifiers comprise latch-type differential amplifiers.
3. The multi-level sensing apparatus of claim 1, wherein the second sense amplifier is enabled after the first sense amplifier is enabled.
4. The multi-level sensing apparatus of claim 1, wherein the first sense amplifier maintains the first output until the second sense amplifier generates the second output.
5. The multi-level sensing apparatus of claim 1, wherein a level of the first reference voltage is between a level of the second reference voltage and a level of the third reference voltage.
6. The multi-level sensing apparatus of claim 1, wherein the reference voltage selector comprises:
a first switching element configured to selectively provide the second reference voltage; and
a second switching element configured to selectively provide the third reference voltage,
wherein the first and second switching elements sharing an output terminal are alternatively turned on or turned off by the first output.
7. The multi-level sensing apparatus of claim 6, wherein the first and second switching elements comprise transmission gates.
8. The multi-level sensing apparatus of claim 6, wherein the reference voltage selector further comprises a stabilizing unit configured to precharge the shared output terminal of the first and second switching elements.
9. The multi-level sensing apparatus of claim 6, wherein the reference voltage selector further comprises a stabilizing unit comprising a capacitor for a voltage stabilization of the shared output terminal of the first and second switching elements.
10. The multi-level sensing apparatus of claim 6, wherein the reference voltage selector further comprises a stabilizing unit comprising a precharging unit configured to precharge the shared output terminal of the first and second switching elements, and a capacitor for a voltage stabilization of the shared output terminal of the first and second switching elements, the precharge unit and the capacitor being coupled in parallel to the shared output terminal of the first and second switching elements.
11. A multi-level sensing method of a non-volatile memory, the multi-level sensing method comprising:
performing a first comparison and amplification operation on a first reference voltage and a read data of a bit line to generate a first output;
selecting one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output;
performing a second comparison and amplification operation on the fourth reference voltage and the read data of the bit line to generate a second output; and
decoding the first and second outputs to output a sensing data.
12. The multi-level sensing method of claim 11, wherein the second comparison and amplification operation is performed after the first comparison and amplification operation.
13. The multi-level sensing method of claim 11, wherein the first output is maintained until the second output is generated.
14. The multi-level sensing method of claim 11, wherein a level of the first reference voltage is between a level of the second reference voltage and a third reference voltage.
15. The multi-level sensing method of claim 11, further comprising precharging an output terminal for the fourth reference voltage before the fourth reference voltage is selected.
16. A sensing apparatus of a phase change memory, the sensing apparatus comprising:
a data driver configured to be selectively turned on for connection to a bit line of the phase change memory and drive a read data of the bit line in the turned-on state;
a first sense amplifier configured to compare the read data transferred through the bit line with a first reference voltage and amplify a comparison result to generate a first output, after the data driver is turned on;
a reference voltage selector configured to select one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output;
a second sense amplifier configured to compare the sensing voltage, the fourth reference voltage, and the read data of the bit line and amplify a comparison result to generate a second output; and
a decoder configured to decode the first and second outputs to output a sensing data.
17. The sensing apparatus of claim 16, wherein the data driver comprises:
a bit line selecting unit configured to selectively transfer the read data loaded on the bit line;
a bit line driving unit configured to selectively drive a sensing voltage; and
a precharging unit disposed between the bit line selecting unit and the bit line driving unit, and configured to precharge an output terminal of the bit line driving unit to the sensing voltage in an interval between the turning-on of the bit line selecting unit and the turning-on of the bit line driving unit.
18. The sensing apparatus of claim 17, wherein the bit line precharging unit comprises;
a switching element configured to selectively couple the bit line selecting unit to the bit line driving unit;
a precharging element disposed between the switching element and the bit line driving unit, and configured to precharge the output terminal of the bit line driving unit to the sensing voltage in an interval between the turning-on of the bit line selecting unit and the turning-on of the bit line driving unit,
wherein the switching element and the precharging element are alternately switched and the switching element is turned on at the same time when the bit line driving unit is turned on.
19. The sensing apparatus of claim 17, wherein the output terminal of the bit line driving unit is coupled to the bit line precharging unit and is shared with input terminals of the first sense amplifier and the second sense amplifier.
20. The sensing apparatus of claim 16, wherein the first and second sense amplifiers comprise latch-type differential amplifiers.
21. The sensing apparatus of claim 16, wherein the second sense amplifier is enabled after the first sense amplifier is enabled.
22. The sensing apparatus of claim 16, wherein the first sense amplifier maintains the first output until the second output of the second sense amplifier is generated.
23. The sensing apparatus of claim 16, wherein a level of the first reference voltage is between a level of the second reference voltage and a level of the third reference voltage.
24. The sensing apparatus of claim 16, wherein the reference voltage selector comprises:
a first switching element configured to selectively provide the second reference voltage; and
a second switching element configured to selectively provide the third reference voltage,
wherein the first and second switching elements sharing an output terminal are alternatively turned on or turned off by the first output.
25. The multi-level sensing apparatus of claim 24, wherein the first and second switching elements comprise transmission gates.
26. The multi-level sensing apparatus of claim 24, wherein the reference voltage selector further comprises a stabilizing unit configured to precharge the shared output terminal of the first and second switching elements.
27. The multi-level sensing apparatus of claim 24, wherein the reference voltage selector further comprises a stabilizing unit comprising a capacitor for a voltage stabilization of the shared output terminal of the first and second switching elements.
28. The multi-level sensing apparatus of claim 24, wherein the reference voltage selector further comprises a stabilizing unit comprising a precharging unit configured to precharge the shared output terminal of the first and second switching elements, and a capacitor for a voltage stabilization of the shared output terminal of the first and second switching elements, which are coupled in parallel to the shared output terminal of the first and second switching elements.
29. A sensing method of a phase change memory, the sensing method comprising:
selecting and precharging a bit line;
driving read data of the bit line after the precharging is completed;
enabling a first sense amplifier to performing a comparison and amplification operation on a first reference voltage and the read data of the bit line to generate a first output;
selecting one of a second reference voltage and a third reference voltage as a fourth reference voltage according to a logic level of the first output;
enabling a second sense amplifier to perform a comparison and amplification operation on the reference voltage and the read data loaded on the bit line to generate a second output; and
decoding the first and second outputs to output a sensing data.
30. The sensing method of claim 29, wherein the second sense amplifier is enabled at a time when the first sense amplifier is enabled.
31. The sensing method of claim 29, wherein the first output is maintained until the second output is generated.
32. The sensing method of claim 29, wherein a level of the first reference voltage is between a level of the second reference voltage and a third reference voltage.
33. The sensing method of claim 29, further comprising precharging the output terminal of the fourth reference voltage before the fourth reference voltage is selected.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a thin film transistor array substrate, the method comprising:
providing a substrate, the substrate having a pixel region and a peripheral circuit region that surrounds the pixel region;
forming a gate pattern on the substrate in the pixel region and forming a first pad pattern on the substrate in the peripheral circuit region;
sequentially forming a gate insulation layer, a semiconductor layer, and a metal layer on the substrate for covering the gate pattern and the first pad pattern;
forming a patterned photoresist layer on the metal layer, wherein the patterned photoresist layer comprises a first resist block, a second resist block, and a third resist block, the first resist block and the second resist block are located above the gate pattern, the first resist block within the pixel region is positioned at opposite sides of the corresponding second resist block, the third resist block has a first opening and corresponds to regions on which the gate pattern is not formed, the first opening is positioned above the first pad pattern, a thickness of the first resist block is greater than a thickness of the second resist block, and the thickness of the second resist block is greater than a thickness of the third resist block;
performing an etching process with use of the patterned photoresist layer as a mask for removing the metal layer, the semiconductor layer, and a portion of the gate insulation layer corresponding to the first opening;
reducing a thickness of the patterned photoresist layer until the third resist block is removed to form a first remaining patterned photoresist layer;
performing an etching process with use of the first remaining patterned photoresist layer as the mask for removing the exposed metal layer and the semiconductor layer;
reducing the thickness of the first remaining patterned photoresist layer until the second resist block is removed to form a second remaining patterned photoresist layer;
performing an etching process with use of the second remaining patterned photoresist layer as the mask for removing the exposed metal layer, a portion of the semiconductor layer, and the gate insulation layer corresponding to the first opening, so as to form a source pattern and a drain pattern respectively at opposite sides of the gate pattern within the pixel region;
removing the second remaining patterned photoresist layer; and
forming a patterned passivation layer on the gate insulation layer for covering the source pattern and the drain pattern, wherein the patterned passivation layer has a second opening in the pixel region, the second opening exposes the corresponding source pattern or the corresponding drain region, the patterned passivation layer has a third opening in the peripheral circuit region, and the third opening exposes the first pad pattern.
2. The method as claimed in 1, further comprising:
forming a pixel electrode on the patterned passivation layer within the pixel region, such that through the corresponding second opening a portion of the pixel electrode is electrically connected to the source pattern or the drain pattern exposed by the corresponding second opening, and a portion of the pixel electrode is electrically connected to the corresponding first pad pattern through the third opening.
3. The method as claimed in claim 1, further comprising forming a first electrode pattern on the substrate within the pixel region before the gate insulation layer and the semiconductor layer are formed on the substrate.
4. The method as claimed in claim 1, wherein a material of the patterned passivation layer is an organic insulation material.
5. The method as claimed in claim 1, wherein the step of forming the patterned photoresist layer on the semiconductor layer comprises:
forming a photoresist material layer on the semiconductor layer; and
patterning the photoresist material layer with use of a half-tone mask or a gray-tone mask, so as to simultaneously form the first resist block, the second resist block, the third resist block, and the first opening.
6. The method as claimed in claim 1, wherein the step of reducing the thickness of the patterned photoresist layer comprises performing an ashing process.
7. The method as claimed in claim 1, wherein the semiconductor layer comprises a channel layer and an ohmic contact layer disposed on the channel layer.
8. The method as claimed in claim 7, wherein the step of forming the source pattern and the drain pattern comprises removing a portion of the channel layer and the ohmic contact layer exposed by the source pattern and the drain pattern.
9. The method as claimed in claim 3, further comprising forming a pixel electrode on the patterned passivation layer within the pixel region, wherein through the corresponding second opening a portion of the pixel electrode is electrically connected to the source pattern or the drain pattern exposed by the corresponding second opening, the patterned passivation layer further has a fourth opening within the pixel region, the fourth opening exposes the gate insulation layer above the first electrode pattern, and through the corresponding fourth opening a portion of the pixel electrode is connected to the gate insulation layer exposed by the corresponding fourth opening.
10. The method as claimed in claim 3, wherein the patterned photoresist layer comprises a fourth resist block positioned above the first electrode pattern, and a thickness of the fourth resist block is substantially equal to the thickness of the first resist block.
11. The method as claimed in claim 10, further comprising etching the metal layer and the semiconductor layer with use of the fourth resist block as the mask and forming a second electrode pattern above the first electrode pattern.
12. The method as claimed in claim 10, wherein the patterned passivation layer has a fourth opening in the pixel region, the fourth opening exposes the corresponding second electrode pattern, and through the corresponding fourth opening the pixel electrode is connected to the second electrode pattern exposed by the corresponding fourth opening.