1. A modular printing device configurable to print with multiple combinations of ink colors and ink types at different print resolutions comprising:
a plurality of printhead arrays, each printhead array being configured to eject ink onto a surface of an image receiving member at a first print resolution in a cross-process direction;
a plurality of ink supplies, each ink supply being configured to store ink and to provide ink to one printhead array in the plurality of printhead arrays; and
a controller configured to operate the plurality of printhead arrays at one of at least two combinations of ink colors and ink types, each combination identifying an ink color or an ink type to be ejected by each printhead array and the controller operating the printhead arrays ejecting a same ink color or a same ink type at a second print resolution in the cross-process direction corresponding to the number of printhead arrays ejecting the same ink color or the same ink type multiplied by the first print resolution.
2. The modular printing device of claim 1, the controller being further configured to control a speed of the image receiving member to eject ink onto the surface of the image receiving member at a predetermined resolution in a process direction.
3. The modular printing device of claim 1 wherein the printhead arrays are configured to form a printed image on the surface of the image receiving member in a single pass of the image receiving member, and the image receiving member is a continuous web of print media.
4. The modular printing device of claim 1 wherein the printhead arrays are configured to form a printed image on the surface of the image receiving member in a single pass of the image receiving member, and the image receiving member is a sheet of print media.
5. The modular printing device of claim 1 wherein the printhead arrays are configured to form a printed image on the surface of the image receiving member in at least two passes of the image receiving member, and the image receiving member is a continuous web of print media.
6. The modular printing device of claim 1 wherein the printhead arrays are configured to form a printed image on the image receiving member in at least two passes of the image receiving member, and the image receiving member is a sheet of print media.
7. A method of operating a modular printing device configured to print with multiple combinations of ink colors and ink types at different print resolutions, the method comprising:
ejecting ink onto a surface of an image receiving member at a first print resolution in a cross-process direction with at least one printhead array of a plurality of printhead arrays;
providing ink to the plurality of printhead arrays with a plurality of ink supplies, each ink supply being configured to store ink and to provide ink to one printhead array in the plurality of printhead arrays;
operating the plurality of printhead arrays at one of at least two combinations of ink colors and ink types with a controller, each combination identifying an ink color or an ink type to be ejected by each printhead array; and
operating the printhead arrays ejecting a same ink color or a same ink type at a second print resolution in the cross-process direction corresponding to the number of printhead arrays ejecting the same ink color or the same ink type multiplied by the first print resolution.
8. The method of operating a modular printing device of claim 7 further comprising:
controlling a speed of the image receiving member with the controller to eject ink onto the surface of the image receiving member at a predetermined print resolution in a process direction.
9. The method of operating a modular printing device of claim 7 further comprising:
forming a printed image on the surface of the image receiving member with the printhead arrays configured to form the printed image in a single pass of the image receiving member, and the image receiving member is a continuous web of print media.
10. The method of operating a modular printing device of claim 7 further comprising:
forming a printed image on the surface of the image receiving member with the printhead arrays configured to form the printed image in a single pass of the image receiving member, and the image receiving member is a sheet of print media.
11. The method of operating a modular printing device of claim 7 further comprising:
forming a printed image on the surface of the image receiving member with the printhead arrays configured to form the printed image in at least two passes of the image receiving member, and the image receiving member is a continuous web of print media.
12. The method of operating a modular printing device of claim 7 further comprising:
forming a printed image on the surface of the image receiving member with the printhead arrays configured to form the printed image in at least two passes of the image receiving member, and the image receiving member is a sheet of print media.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device comprising:
a first and a second signal line forming a pair of signal lines;
a third and a fourth signal line forming another pair of signal lines;
a memory cell connected to the first and second signal lines; and
a sense amplifier circuit provided between the first and second signal lines and the third and fourth signal lines,
wherein
the sense amplifier circuit includes
a first transistor of a first conductivity type having a gate connected to a precharge signal, a source connected to a first power supply potential, and a drain connected to the first signal line,
a second transistor of the first conductivity type having a gate connected to the precharge signal, a source connected to the first power supply potential, and a drain connected to the second signal line,
a third transistor of the first conductivity type having a gate connected to the first signal line, a source connected to the first power supply potential, and a drain connected to the third signal line,
a fourth transistor of the first conductivity type having a gate connected to the second signal line, a source connected to the first power supply potential, and a drain connected to the fourth signal line,
a fifth transistor of a second conductivity type having a gate connected to the third signal line, a source connected to a second power supply potential, and a drain connected to the first signal line, and
a sixth transistor of the second conductivity type having a gate connected to the fourth signal line, a source connected to the second power supply potential, and a drain connected to the second signal line.
2. The semiconductor memory device of claim 1, wherein
the first and second signal lines are local bit lines,
the third and fourth signal lines are global bit lines,
the local and global bit lines form a hierarchical bit line architecture.
3. The semiconductor memory device of claim 1, wherein
the memory cell includes
a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,
a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,
a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a word line, and
a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to the word line.
4. The semiconductor memory device of claim 1, wherein
the memory cell includes
a first cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to a first memory node, and a gate connected to a second memory node,
a second cell transistor of the first conductivity type having a source connected to the first power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a third cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the first memory node, and a gate connected to the second memory node,
a fourth cell transistor of the second conductivity type having a source connected to the second power supply potential, a drain connected to the second memory node, and a gate connected to the first memory node,
a fifth cell transistor of the second conductivity type having a source connected to the first memory node, a drain connected to the first signal line, and a gate connected to a first word line, and
a sixth cell transistor of the second conductivity type having a source connected to the second memory node, a drain connected to the second signal line, and a gate connected to a second word line different from the first word line.
5. The semiconductor memory device of claim 1, wherein
the sense amplifier circuit further includes
a seventh transistor of the second conductivity type having a drain connected to the sources of the fifth and sixth transistors, a source connected to the second power supply potential, and a gate connected to a control signal derived from a column selection signal.
6. The semiconductor memory device of claim 1, wherein
the potential value of the second power supply potential connected to the sources of the fifth and sixth transistors is controlled based on a control signal derived from a column selection signal.
7. A semiconductor memory device comprising:
memory cells;
bit lines each connected to corresponding ones of the memory cells; and
sense amplifier circuits each connected to corresponding ones of the bit lines,
wherein
each of the sense amplifier circuits has a single-end configuration and a function of writing data read from a corresponding one of the memory cells back to the corresponding bit lines, and achieves data write operation to a corresponding one of the memory cells by the function of writing data back to the corresponding bit lines.
8. The semiconductor memory device of claim 7, wherein
the bit lines have a hierarchical architecture divided in memory cell arrays.
9. The semiconductor memory device of claim 7, wherein
the function of writing data back to the bit line is a function of writing back one of high data and low data.
10. The semiconductor memory device of claim 7, wherein
each of the sense amplifier circuits is provided between separated memory cell arrays.
11. The semiconductor memory device of claim 10, wherein
two of the sense amplifier circuits connected to two separated ones of the bit lines are arranged adjacent to each other.