1460954193-73940d2b-7069-4caf-8585-af3d56e255ae

1. A fuel cell for production of electrical energy, comprising
a fuel chamber (1)
an anode (2a),
a cathode (2b),
an electrolyte (3) disposed between said anode and said cathode,
an oxidant chamber (4), wherein said chambers (1) and (4) enclose said anode, cathode and electrolyte,
wherein said electrolyte (3) is a ceramic CSC (ceria salt composite) electrolyte with an operating temperature range of 300\xb0\u2013800\xb0 C. and comprising at least one salt and at least one ceria phase, and
wherein the electrolyte is sulphate-based CSC for sulphur containing fuels, intended to operate as a high sulphur tolerant CFC device, acting as a pre-gas treatment station and intended to be combined with MCFC power plants.
2. A fuel cell according to claim 1, wherein the electrolyte comprises salts selected from salts that makes the CSC material function as a specific conductor for particular ions.
3. A fuel cell according to claim 1, wherein the electrodes comprise binary oxides selected from the group of binary oxides consisting of: AxByOz (A, B=Li, Mg, Ca, Sr, Cr, Fe, Co, Ni, Mn, Cu, Y, La, Ce, Zr, or Ti).
4. A fuel cell according to claim 2, wherein the electrodes comprise binary oxides selected from the group of binary oxides consisting of: AxByOz (A, B=Li, Mg, Ca, Sr, Cr, Fe, Co, Ni, Mn, Cu, Y, La, Ce, Zr, or Ti).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A passive device, comprising:
a substrate;
a stack on the substrate, the stack comprising alternating dielectric layers and conductive layers the conductive layers comprise a bottom conductive layer and one other conductive layer, and the stack comprises a plurality of vertically-extending holes filled with oxide-nitride-oxide layers;
an above-stack metal layer, above the stack;
a first contact structure which extends up from the bottom conductive layer to the above-stack metal layer; and
a second contact structure which extends up from the one other conductive layer to the above-stack metal layer, the bottom conductive layer and the one other conductive layer are conductive plates of a capacitor and are connected in parallel to the above-stack metal layer by the first contact structure and the second contact structure.
2. The passive device of claim 1, further comprising:
a below-stack metal layer, below the stack;
a contact structure which extends from the below-stack metal layer to the above-stack metal layer; and
circuitry direct below the stack, connected to the below-stack metal layer.
3. The passive device of claim 1, wherein:
the passive device is in a peripheral area of a 3D stacked non-volatile memory device, lateral of a cell area of the substrate; and
the cell area comprises rows of vertical columns of NAND cells.
4. The passive device of claim 1, wherein:
the stack comprises a terraced portion at which the bottom conductive layer touches the first contact structure, and at which the one other conductive layer touches the second contact structure.
5. The passive device of claim 1, wherein:
the conductive layers comprise metal silicide.
6. The passive device of claim 1, wherein:
the stack comprises an insulation-filled slit which extends from a bottom of the stack to a top of the stack.
7. A passive device, comprising:
a substrate;
a stack on the substrate, the stack comprises alternating dielectric layers and conductive layers, and a plurality of vertically-extending holes filled with oxide-nitride-oxide layers;
an above-stack metal layer, above the stack; and
contact structures which extend up from the conductive layers to the above-stack metal layer, the conductive layers are conductive plates of a capacitor and are connected in parallel to the above-stack metal layer by the contact structures.
8. The passive device of claim 7, wherein:
the stack comprises an insulation-filled slit which extends from a bottom of the stack to a top of the stack.
9. The passive device of claim 7, wherein:
the passive device is in a peripheral area of a 3D stacked non-volatile memory device, lateral of a cell area of the substrate.