What is claimed is:
1. A floating point maxmin circuit for determining a threshold condition between two floating point operands, comprising:
a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand;
a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand;
a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal; and
a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal.
2. The floating point maxmin circuit of claim 1 further comprising:
a first operand buffer coupled to the first analysis circuit, the first operand buffer supplying the first floating point operand to the first analysis circuit; and
a second operand buffer coupled to the second analysis circuit, the second operand buffer supplying the second floating point operand to the second analysis circuit.
3. The floating point maxmin circuit of claim 1, wherein the format is from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero.
wherein the normalized and denormalized formats indicate a finite numerical value.
4. The floating point maxmin circuit of claim 3, wherein the decision circuit treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates positive infinity, and
wherein the decision circuit treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates a finite numerical value.
5. The floating point maxmin circuit of claim 3, wherein the decision circuit treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative infinity, and
wherein the decision circuit treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates a finite numerical value.
6. The floating point maxmin circuit of claim 3, wherein the decision circuit treats the first floating point operand as greater than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates positive zero, and
wherein the decision circuit treats the first floating point operand as less than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates a positive finite numerical value.
7. The floating point maxmin circuit of claim 3, wherein the decision circuit treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative zero, and
wherein the decision circuit treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative underflow and the format of the second floating point operand indicates a negative finite numerical value.
8. The floating point maxmin circuit of claim 3, wherein the floating point maxml circuit obeys a commutative law of arithmetic when the format of at least one of the two floating point operands indicates not-a-number (NaN).
9. The floating point maxmin circuit of claim 3, wherein the floating point maxmin circuit obeys an associative law of arithmetic when the format of at least one of the two floating point operands indicates not-a-number (NaN).
10. The floating point maxmin circuit of claim 3, wherein if the status of at least one of the two floating point operands indicates not-a-number (NaN), then the decision circuit obeys the identities:
max(x,y)min(x,y) and min(x,y)max(x,y);
wherein x represents a value of first floating point operand and y represents a value of the second floating point operand, and
wherein the negation operation x complements the sign bit of x.
11. The floating point maxmin circuit of claim 3, wherein if the format of at least one of the floating point operands indicates not-a-number (NaN), then the decision circuit obeys the identities:
max(min(x,y), min(x,z))min(x,max(y,z)), and min(max(x,y), max(x,z))max(x,min(y,z));
wherein x represents a value of the first floating point operand, y represents a first value of the second floating point operand, and z represents a second value of the second floating point operand.
12. The floating point maxmin circuit of claim 3, wherein if the respective formats of the two floating point operands indicate not-a-number (NaN), then the decision circuit dynamically determines which of the two NaN floating point operands to represent in the result.
13. The floating point maxmin circuit of claim 3, wherein if the respective formats of the two floating point operands indicate not-a-number (NaN), then the floating-point maxmin circuit produces the result using the floating point status information from the one of the two floating point operands having a larger fraction.
14. The floating point maxmin circuit of claim 3, wherein the result is a third floating point operand having encoded floating point status information.
15. The floating point maxmin circuit of claim 14, wherein at least part of the encoded floating point status information in the result comes from at least one of: the first floating point operand and the second floating point operand.
16. The floating point maxmin circuit of claim 14, wherein the encoded floating point status information in the result further comprises overflow status information if the encoded floating point status information of one of the two floating point operands indicates overflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
17. The floating point maxmin circuit of claim 14, wherein the encoded floating point status information in the result further comprises underflow status information if the encoded floating point status information of one of the two floating point operands indicates underflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
18. The floating point maxmin circuit of claim 14, wherein the encoded floating point status information in the result further comprises inexact status information if the encoded floating point status information of one of the two floating point operands indicates overflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
19. The floating point maxmin circuit of claim 14, wherein the encoded floating point status information in the result further comprises inexact status information if the encoded floating point status information of one of the two floating point operands indicates underflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
20. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates infinity, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
21. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates overflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and overflow status information.
22. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates underflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and underflow status information.
23. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates overflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and inexact status information.
24. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates underflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and inexact status information.
25. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates NaN, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
26. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates infinity, then the result produced contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
27. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates overflow, then the result produced is a copy of the first floating point operand in the infinity format.
28. The floating point maxmin circuit of claim 14, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates overflow, then the result produced is a copy of the first floating point operand in the infinity format.
29. A method for providing one of the maximum and the minimum of a first floating point operand and a second floating point operand, comprising:
receiving the first floating point operand;
receiving the second floating point operand;
determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand;
determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and
producing a result indicating which of the floating point operand and the second floating point operand is larger or smaller than the other, based on the first format and the second format.
30. The method of claim 29 further comprising:
receiving at least one control signal that causes the result to indicate one of: the maximum of the first and second floating point operands and the minimum of the first and second floating point operands.
31. The method of claim 29, wherein the format determined for the first floating point operand and the format determined for the second floating point are from a group comprising:
not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero.
32. The method of claim 29, wherein the format represents one of a positive overflow (OV) and a negative overflow (OV).
33. The method of claim 29, wherein the format represents one of a positive underflow (UN) and a negative underflow (UN).
34. The method of claim 29, wherein the format represents one of a positive infinity and a negative infinity.
35. The method of claim 29, wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates positive infinity, and
wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates a finite numerical value.
36. The method of claim 29, wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative infinity, and
wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates a finite numerical value.
37. The method of claim 29, wherein the step of producing a result treats the first floating point operand as greater than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates positive zero, and
wherein the step of producing a result treats the first floating point operand as less than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates a positive finite numerical value.
38. The method of claim 29, wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative zero, and
wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative underflow and the format of the second floating point operand indicates a negative finite numerical value.
39. The method of claim 29, wherein the step of producing a result further comprises:
obeying a commutative law of arithmetic when the format of at least one of the two floating point operands indicates not-a-number (NaN).
40. The method of claim 29, wherein the step of producing a result further comprises:
obeying an associative law of arithmetic if the format of at least one of the two floating point operands indicates not-a-number (NaN).
41. The method of claim 29, wherein if the status of at least one of the two floating point operands indicates not-a-number (NaN), then the step of producing a result obeys the identities:
max(x,y)min(x,y)andmin(x,y)max(x,y);
wherein x represents the first floating point operand and y represents the second floating point operand, and
wherein the negation operation x complements the sign bit of x.
42. The method of claim 29, wherein if the format of at least one of the floating point operands indicates not-a-number (NaN), then the step of producing a result obeys the identities:
max(min(x,y), min(x,z))min(x,max(y,z)), and min(max(x,y), max(x,z))max(x,min(y,z));
wherein x represents the first floating point operand, y represents the second floating point operand, and z represents a third floating point operand.
43. The method of claim 29, wherein if the respective formats of the two floating point operands indicate not-a-number (NaN), then the step of producing the result further comprises the step of:
using the floating point status information from the one of the two floating point operands having a larger fraction to produce the result.
44. The method of claim 29, wherein the result is a third floating point operand having encoded floating point status information.
45. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates infinity, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
46. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates overflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and overflow status information.
47. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates underflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and underflow status information.
48. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates overflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and inexact status information.
49. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates underflow, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and inexact status information.
50. The method of claim 44, wherein if the format of the first floating point operand indicates NaN and the format of the second floating point operand indicates NaN, then the result produced is in the NaN format and contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
51. The method of claim 44, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates infinity, then the result produced contains floating point status information that is a combination of the floating point status information encoded within the first floating point operand and the floating point status information encoded within the second floating point operand.
52. The method of claim 44, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates overflow, then the result produced is a copy of the first floating point operand in the infinity format.
53. The method of claim 44, wherein if the format of the first floating point operand indicates infinity and the format of the second floating point operand indicates overflow, then the result produced is a copy of the first floating point operand in the infinity format.
54. The method of claim 44, wherein at least part of the encoded floating point status information in the result comes from at least one of: the first floating point operand and the second floating point operand.
55. The method of claim 54, wherein the encoded floating point status information in the result further comprises overflow status information if the encoded floating point status information of one of the two floating point operands indicates overflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
56. The method of claim 54, wherein the encoded floating point status information in the result further comprises underflow status information if the encoded floating point status information of one of the two floating point operands indicates underflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
57. The method of claim 54, wherein the encoded floating point status information in the result further comprises inexact status information if the encoded floating point status information of one of the two floating point operands indicates overflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
58. The method of claim 54, wherein the encoded floating point status information in the result further comprises inexact status information if the encoded floating point status information of one of the two floating point operands indicates underflow status and the encoded floating point status information of the other of the two floating point operands indicates at least one of: an infinity status and a NaN status.
59. A computer-readable medium on which is stored a set of instructions for providing the maximum or minimum of first floating point operand and a second floating point operand, which when executed perform steps comprising:
receiving the first floating point operand;
receiving the second floating point operand;
determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand;
determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and
producing a result indicating which of the floating point operand and the second floating point operand is larger or smaller than the other, based on the first format and the second format.
60. The computer-readable medium of claim 59, wherein the format determined for the first floating point operand and the format determined for the second floating point are from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero.
61. The computer-readable medium of claim 59, wherein the result is a third floating point operand having encoded floating point status information.
62. The computer-readable medium of claim 59, wherein at least part of the encoded floating point status information in the result comes from at least one of: the first floating point operand and the second floating point operand.
63. The computer-readable medium of claim 59, wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates positive infinity, and
wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates positive overflow and the format of the second floating point operand indicates a finite numerical value.
64. The computer-readable medium of claim 59, wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative infinity, and
wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates a finite numerical value.
65. The computer-readable medium of claim 59, wherein the step of producing a result treats the first floating point operand as greater than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates positive zero, and
wherein the step of producing a result treats the first floating point operand as less than a second floating point operand if the format of the first floating point indicates positive underflow and the format of the second floating point operand indicates a positive finite numerical value.
66. The computer-readable medium of claim 59, wherein the step of producing a result treats the first floating point operand as less than the second floating point operand if the format of the first floating point indicates negative overflow and the format of the second floating point operand indicates negative zero, and
wherein the step of producing a result treats the first floating point operand as greater than the second floating point operand if the format of the first floating point indicates negative underflow and the format of the second floating point operand indicates a negative finite numerical value.
67. The computer-readable medium of claim 59, wherein the step of producing a result further comprises:
obeying a commutative law of arithmetic when the format of at least one of the two floating point operands indicates not-a-number (NaN).
68. The computer-readable medium of claim 59, wherein the step of producing a result further comprises:
obeying an associative law of arithmetic if the format of at least one of the two floating point operands indicates not-a-number (NaN).
69. The computer-readable medium of claim 59, wherein if the status of at least one of the two floating point operands indicates not-a-number (NaN), then the step of producing a result obeys the identities:
max(x,y)min(x,y) and min(x,y)max(x,y);
wherein x represents the first floating point operand and y represents the second floating point operand, and
wherein the negation operation x complements the sign bit of x.
70. The computer-readable medium of claim 59, wherein if the format of at least one of the floating point operands indicates not-a-number (NaN), then the step of producing a result obeys the identities:
max(min(x,y), min(x,z))min(x,max(y,z)), and min(max(x,y), max(x,z))max(x,min(y,z));
wherein x represents the first floating point operand, y represents the second floating point operand, and z represents a third floating point operand.
71. The computer-readable medium of claim 59, wherein if the respective formats of the two floating point operands indicate not-a-number (NaN), then the step of producing the result further comprises the step of:
using the floating point status information from the one of the two floating point operands having a larger fraction to produce the result.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A stent comprising:
a first loop containing section arranged in a circumferential direction and defining loops therein occurring at a first frequency;
a second loop containing section arranged in the circumferential direction and defining loops therein occurring at the first frequency;
a third loop containing section disposed in a generally circumferential space between the first loop containing section and the second loop containing section and coupling the first loop containing section to the second loop containing section for defining cells therebetween, the third loop containing section defining loops therein occurring at a second frequency that is greater than the first frequency.
2. The stent according to claim 1, wherein the first and second loop containing sections are each part of a continuous circumferential member having a plurality of the first and second loop containing sections respectively and the third loop containing section is also part a continuous loop having a plurality of the third loop containing sections coupled to first and second loop containing sections for defining the cells.
3. The stent according to claim 1, wherein the first and second loop containing sections are each part of a continuous circumferential member having a plurality of the first and second loop containing sections respectively and wherein a plurality of the third loop containing sections each having one end connected to one of the first loop containing sections and another end connected to one of the second loop containing sections are provided.
4. The stent according to claim 1, wherein the first loop containing section and the second loop containing section are 180 degrees out of phase with one another.
5. The stent according to claim 2, wherein the first loop containing section and the second loop containing section are 180 degrees out of phase with one another.
6. The stent according to claim 3, wherein the first loop containing section and the second loop containing section are 180 degrees out of phase with one another.
7. The stent according to claim 6, wherein one end of each of the third loop containing sections is connected to a first loop the first loop containing section, and another end of each of the flexible compensating members is connected to a second loop of the second loop containing section, said second loop being circumferentially offset with respect to the first loop.
8. The stent according to claim 7, wherein the third loop containing section has a width than is smaller than a width of the first loop containing section and of the second loop containing section.
9. A stent comprising:
first meander patterns having axes extending in a first direction;
second meander patterns having axes extending in a second direction that is different from the first direction;
wherein the second meander patterns are intertwined with the first meander patterns; and
wherein the second meander patterns have loop portions with at least one loop, each loop portion having one end connected to one of first meander patterns and another end connected to a neighboring one of the first meander patterns such that said one end of said each loop portion is circumferentially offset with respect to said another end of said each loop portion.
10. The stent according to claim 8, wherein each loop portion has at least two loops.
11. The stent according to claim 9, wherein the loop portions of the second meander patterns have a smaller width than the first meander patterns.
12. A stent formed of a tube having a patterned shape, the patterned shape in the expanded and deployed state comprising:
a) first meander patterns, having axes extending in a first direction;
b) second meander patterns having axes extending in a second direction different from said first direction, wherein said second meander patterns are intertwined with said first meander patterns to form a generally uniform distributed structure;
d) wherein said first meander patterns are connected to said second meander patterns so as to a leave a portion of said second meander patterns between each first meander pattern;
e) wherein said second meander patterns are connected to said first meander patterns so as to leave loops of said first meander patterns between each pair of second meander patterns; and
f) wherein said second meander patterns have loop portions with at least one loop, each loop portion having one end connected to one of first meander patterns and another end connected to a neighboring one of the first meander patterns such that said one end of said each loop portion is circumferentially offset with respect to said another end of said each loop portion.
13. A stent according to claim 12 wherein said first meander patterns have loops, and wherein said second meander patterns are connected to said first meander patterns so as to leave one loops of said first meander patterns between each pair of second meander patterns.
14. A stent according to any preceding claim, wherein the first meander patterns comprise even first meander patterns and odd first meander patterns and wherein the odd first meander patterns are 180 out of phase with the even first meander patterns and occur between every two even first meander patterns.
15. A stent comprising:
a. at least odd and even alternating serpentine sections, each having first areas of inflection, wherein said odd serpentine section is out of phase from said even serpentine section such that first areas of inflection on said odd serpentine section are adjacent first areas of inflection on said even serpentine section; and
b. a plurality of flexible connectors, one located between each first area of inflection of one of said odd and even alternating serpentine sections and a first area of inflection of the other of said odd even alternating serpentine sections which is circumferentially offset from said first area of inflection of one of said odd and even alternating serpentine sections, wherein said flexible connector has at least two portions connected by at least one second area of inflection, and wherein said first and second areas of inflection define first and second angles whose bisecting lines are substantially parallel to one another.
16. A stent according to claim 15, wherein said flexible connectors are part of a continuous additional serpentine section.
17. A stent according to claim 15, wherein said flexible connectors are separate elements.