1. A method of determining a pumping torque of an internal combustion engine having a predetermined air induction configuration, comprising the steps of:
determining an engine speed, an engine delta pressure, and a relative engine airload;
calculating a first contribution based on the engine delta pressure using first predetermined data, the first contribution corresponding to throttling loss;
calculating a second contribution based on the engine speed and the engine airload using second predetermined data, the second contribution corresponding to valve flow loss; and
determining a pumping torque based on the first and second contributions.
2. The method of claim 1 wherein said step of determining engine delta pressure comprises the substeps of:
determining an air intake pressure (Pint);
determining an exhaust pressure (Pexh);
determining a difference between the intake and exhaust pressures (Pexh-Pint).
3. The method of claim 1 wherein said step of determining the engine airload comprises the substeps of:
determining a reference cylinder air mass taken at a predetermined volumetric efficiency (VE), predetermined intake pressure and predetermined temperature;
determining an actual cylinder air mass; and
dividing the actual cylinder air mass by the reference cylinder air mass to obtain the engine airload (%).
4. The method of claim 1 said step of determining the first contribution includes the substep of:
obtaining a first pumping mean effective pressure (PMEP) value from a first data structure containing the first predetermined data based on the engine pressure delta.
5. The method of claim 4 wherein said step of determining the second contribution includes the substep of:
obtaining a second pumping mean effective pressure (PMEP) value from a second data structure containing the second predetermined data based on the engine speed and the engine airload.
6. The method of claim 5 wherein said step of determining the pumping torque includes the sub-steps of:
summing the first and second PMEP values to obtain an aggregate PMEP value; and
multiplying the aggregate PMEP value by a predetermined conversion factor to obtain the pumping torque.
7. The method of claim 6 wherein the predetermined conversion factor corresponds to Veng4*\u03c0 where Veng is the total displacement volume of the engine.
8. A method of controlling an internal combustion engine having a predetermined air induction configuration, comprising the steps of:
determining an engine speed, an engine delta pressure, and a relative engine airload;
calculating a first contribution based on the engine delta pressure using first predetermined data, the first contribution corresponding to throttling loss;
calculating a second contribution based on the engine speed and the engine airload using second predetermined data, the second contribution corresponding to valve flow loss;
determining a pumping torque based on the first and second contributions; and
controlling the engine based on the determined pumping torque.
9. The method of claim 8 wherein said step of determining engine delta pressure comprises the substeps of:
determining an air intake pressure (Pint);
determining an exhaust pressure (Pexh);
determining a difference between the intake and exhaust pressures (Pexh-Pint).
10. The method of claim 8 wherein said step of determining the engine airload comprises the substeps of:
determining a reference cylinder air mass taken at a predetermined volumetric efficiency (VE), predetermined intake pressure and predetermined temperature;
determining an actual cylinder air mass; and
dividing the actual cylinder air mass by the reference cylinder air mass to obtain the engine airload (%).
11. The method of claim 8 said step of determining the first contribution includes the substep of:
obtaining a first pumping mean effective pressure (PMEP) value from a first data structure containing the first predetermined data based on the engine pressure delta.
12. The method of claim 11 wherein said step of determining the second contribution includes the substep of:
obtaining a second pumping mean effective pressure (PMEP) value from a second data structure containing the second predetermined data based on the engine speed and the engine airload.
13. The method of claim 12 wherein said step of determining the pumping torque includes the sub-steps of:
summing the first and second PMEP values to obtain an aggregate PMEP value; and
multiplying the aggregate PMEP value by a predetermined conversion factor to obtain the pumping torque.
14. The method of claim 13 wherein the predetermined conversion factor corresponds to Veng4*\u03c0 where Veng is the total displacement volume of the engine.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An active bias circuit for providing a biasing voltage to an electrical circuit formed on a wafer, the active bias circuit comprising a field effect transistor (FET) having a channel connected to its gate, a biasing current flowing through the FET sets the biasing voltage at the gate of the FET, the FET being formed on the wafer which the electrical circuit is formed to proportionally compensate for variations in the electrical circuit and the active bias circuit as a result of wafer lot to wafer lot variations.
2. The active bias circuit of claim 1 wherein an output of the electrical circuit is connected to the channel of the FET.
3. The active bias circuit of claim 2 wherein the output of the electrical circuit is a radio frequency signal.
4. The active bias circuit of claim 1 wherein the FET may be selected from the group consisting of JFET, MOSFET, MESFET, and HEMT.
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. An amplifier comprising:
a. at least one transistor having an input operative to receive an input signal and amplify the input signal to an output signal which is delivered to an output; and
b. an active bias circuit comprising a field effect transistor (FET) having a channel connected to its gate, a biasing current flowing through the FET sets a biasing voltage at the gate of the FET, the FET is connected to the transistor so as to bias the input signal.
10. The amplifier circuit of claim 9 wherein the transistor is formed on a wafer and the active bias circuit is formed on the wafer which the transistor is formed to proportionally compensate for variations in the transistor and the active bias circuit as a result of wafer lot to wafer lot variations.
11. The amplifier of claim 9 wherein the output signal provides the biasing current to the FET.
12. The amplifier of claim 10 wherein the output signal is a radio frequency signal.
13. The amplifier of claim 9 wherein the FET has a N- type channel.
14. The amplifier of claim 9 wherein the FETs may be selected from the group consisting of JFET, MOSFET, MESFET, HEMT and pHEMT.
15. The amplifier of claim 9 wherein the active bias circuit has high impedance such that the active bias circuit is transparent to the transistor.
16. An amplifier comprising:
a. at least one transistor having an input operative to receive an input signal and to amplify the input signal to an output signal which is delivered to an output, the transistor being formed on a wafer; and
b. an active bias circuit comprising first and second field effect transistors (FETs), each FET having a channel connected to a gate of the other FET to regulate an amount of current flowing through the channels of the first and second FETs, a current flowing through the second FET sets the biasing voltage at the gate of the first FET, the active bias circuit being formed on the wafer to proportionally compensate for variations in the transistor and the active bias circuit as a result of wafer lot to wafer lot variations.
17. (canceled)
18. The amplifier of claim 16 further comprising a resistive voltage divider connected to the channel of first FET to adjust the biasing voltage at the gate of the first FET.
19. The amplifier of claim 16 comprising a sink circuit connected to the gate of the first FET to sink any leakage current from the transistor.
20. The amplifier of claim 18 wherein the sink circuit is a resistor and at least one diode connected in series.
21. An electrical circuit comprising:
a. a transistor formed on a wafer having a designed input biasing voltage for operating the transistor in an optimal range, the transistor having a required input biasing voltage offset to operate the transistor in the optimal range due to wafer lot variations; and
b. an active bias circuit formed on the wafer in electrical communication with the transistor, the active bias circuit having a designed output biasing voltage and an actual output biasing voltage offset due to the wafer lot variations, the actual output biasing voltage offset being proportional to the required input biasing voltage offset of the transistor such that the amplifier circuit operates in the optimal range, notwithstanding wafer lot variations.
22. The electrical circuit of claim 21 wherein the active bias circuit comprises:
i) first and second field effect transistors (FETs), each FET having a channel connected to a gate of the other FET to regulate an amount of current flowing through the channels of the first and second FETs, the source of the second FET connected to the input of the transistor to bias the transistor with the biasing voltage;
ii. wherein an actual current draw of the transistor and FETs of the active bias circuit is greater or less than the designed current draw of the transistor and FETS due to wafer lot variations, and the increased or decreased current draw through the first FET produces a lower or higher voltage, respectively, at the gate of the second FET to respectively reduce or increase the voltage at the source of the second FET such that the actual output biasing voltage of the active bias circuit has compensated for wafer lot variations.
23. An electrical circuit comprising:
a. a wafer
b. an electrical circuit formed on the wafer;
c. an active bias circuit formed on the wafer to compensate for variations in the electrical circuit and the active bias circuit as a result of wafer lot to wafer lot variations.
24. The electrical circuit of claim 23 wherein the active bias circuit comprises
i. first and second field effect transistors (FETs), each FET having a channel connected to a gate of the other FET to regulate an amount of current flowing through the channels of the first and second FETs, a current flowing through the second FET sets the biasing voltage at the gate of the first FET.