1. A receiving apparatus comprising:
a clock unit that outputs time information;
a synchronizing (sync) packet receiving unit that receives a sync packet which contains transmitting time information and which is sent from a transmitting apparatus over an asynchronous network;
a magnitude-of-jitter calculation unit that calculates as a magnitude of a jitter a difference between a first difference, which is a difference between the receiving times of two adjoining sync packets received by the sync packet receiving unit, and a second difference which is a difference between the transmitting times of the two sync packets;
a delay time estimation unit that obtains the delay time of the sync packet on the basis of magnitudes of jitters calculated by the magnitude-of-jitter calculation unit; and
a time correction unit that compensates the transmitting time of the sync packet, which is received by the sync packet receiving unit, on the basis of the delay time of the sync packet, which is obtained by the delay time estimation unit, so as to obtain a compensated time, and rewrites and corrects the time of the clock unit with the compensated time.
2. The receiving apparatus according to claim 1, wherein the delay time estimation unit comprises:
a cumulative summation block that cumulates and summates magnitudes of jitters calculated by the magnitude-of-jitter calculation unit so as to obtain a cumulative summation value of magnitudes of jitters;
a minimum value detection block that detects the minimum value of the cumulative summation values of magnitudes of jitters obtained by the cumulative summation block; and
a shift block that shifts the cumulative summation value of magnitudes of jitters, which is obtained by the cumulative summation block, so that the minimum value detected by the minimum value detection block will be equal to the minimum value of delay times, and thus obtains the delay time of the sync packet.
3. The receiving apparatus according to claim 2, wherein:
the delay time estimation unit further includes a validity-of-estimation decision block that outputs a decision signal which validates a period during which the cumulative summation value of magnitudes of jitters obtained by the cumulative summation block is the minimum value detected by the minimum value detection block, and invalidates the other period; and
during the period validated with the decision signal outputted from the validity-of-estimation decision block, the time correction unit rewrites and corrects the time of the clock unit with the compensated time.
4. The receiving apparatus according to claim 2, wherein:
the delay time estimation unit further includes a designation block that designates a minimum-value range for magnitudes of jitters on the basis of at least the minimum value of the magnitudes of jitters calculated by the magnitude-of-jitter calculation unit, and a validity-of-estimation decision block that outputs a decision signal which validates a period during which the magnitude of a jitter calculated by the magnitude-of-jitter calculation unit falls within the minimum-value range designated by the designation block, and invalidates the other period; and
during the period validated with the decision signal outputted from the validity-of-estimation decision block, the time correction unit rewrites and corrects the time of the clock unit with the compensated time.
5. The receiving apparatus according to claim 2, wherein the minimum value of delay times employed by the shift block is a fixed value measured and determined in advance.
6. The receiving apparatus according to claim 2, wherein the minimum value of delay times employed by the shift block is a varying value measured and determined by a delay time measurement section.
7. The receiving apparatus according to claim 6, wherein the delay time measurement section calculates as a delay time a difference between a first time, which is a time at which a delay-request packet is transmitted to the transmitting apparatus, and a second time that is a time which is represented with time information contained in the delay-response packet received from the transmitting apparatus responsively to the transmission of the delay-request packet and at which the transmitting apparatus receives the delay-request packet, and detects the minimum value of such delay times as the minimum value of delay times.
8. The receiving apparatus according to claim 2, wherein:
the delay time estimation unit includes a switch that selectively fetches the minimum value of delay times which is a fixed value measured and determined in advance, or the minimum value of delay times which is a varying value measured and determined by the delay time measurement section; and
the minimum value of delay times employed by the shift block is the minimum value of delay times fetched by the switch.
9. The receiving apparatus according to claim 1, wherein:
the delay time estimation unit includes
a cumulative summation block that cumulates and summates magnitudes of jitters calculated by the magnitude-of-jitter calculation unit so as to obtain a cumulative summation value of magnitudes of jitters,
a minimum value detection block that detects the minimum value of the cumulative summation values of magnitudes of jitters obtained by the cumulative summation block,
a validity-of-estimation decision block that outputs a decision signal which validates a period during which the cumulative summation value of magnitudes of jitters obtained by the cumulative summation block is the minimum value detected by the minimum value detection block, and invalidates the other period, and
an output block that during the period validated with the decision signal outputted from the validity-of-estimation decision block, outputs the minimum value of delay times as the delay time of a sync packet; and
during the period validated with the decision signal outputted from the validity-of-estimation decision block, the time correction unit rewrites and corrects the time of the clock unit with the compensated time.
10. The receiving apparatus according to claim 9, wherein the minimum value of delay times employed by the output block is a fixed value measured and determined in advance.
11. The receiving apparatus according to claim 9, wherein the minimum value of delay times employed by the output block is a varying value measured and determined by the delay time measurement section.
12. The receiving apparatus according to claim 9, wherein:
the delay time estimation unit includes a switch that selectively fetches the minimum value of delay times which is a fixed value measured and determined in advance, or the minimum value of delay times which is a varying value measured and determined by the delay time measurement section; and
the minimum value of delay times employed by the output block is the minimum value of delay times fetched by the switch.
13. The receiving apparatus according to claim 1, wherein:
the delay time estimation unit includes
a designation block that designates a minimum-value range for magnitudes of jitters on the basis of at least the minimum value of the magnitudes of jitters calculated by the magnitude-of-jitter calculation unit,
a validity-of-estimation decision block that outputs a decision signal which validates a period during which the magnitude of a jitter calculated by the magnitude-of-jitter calculation unit falls within the minimum-value range designated by the designation block, and invalidates the other period, and
an output block that outputs the minimum value of delay times as the delay time of a sync packet during the period validated with the decision signal outputted from the validity-of-estimation decision block; and
during the period validated with the decision signal outputted from the validity-of-estimation decision block, the time correction unit rewrites and corrects the time of the clock unit with the compensated time.
14. The receiving apparatus according to claim 13, wherein the minimum value of delay times employed by the output block is a fixed value measured and determined in advance.
15. The receiving apparatus according to claim 13, wherein the minimum value of delay times employed by the output block is a varying value measured and determined by the delay time measurement section.
16. The receiving apparatus according to claim 13, wherein:
the delay time estimation unit includes a switch that selectively fetches the minimum value of delay times, which is a fixed value measured and determined in advance, or the minimum value of delay times which is a varying value measured and determined by the delay time measurement section; and
the minimum value of delay times employed by the output block is the minimum value of delay times fetched by the switch.
17. A time correction method for a receiving apparatus including a clock unit that outputs time information, comprising the steps of:
receiving a sync packet that contains transmitting time information and is sent from a transmitting apparatus over an asynchronous network;
calculating as a magnitude of a jitter a difference between a first difference, which is a difference between the receiving times of two adjoining sync packets received at the sync packet receiving step, and a second difference that is a difference between the transmitting times of the two sync packets;
obtaining the delay time of the sync packet on the basis of the magnitudes of jitters calculated at the magnitude-of-jitter calculating step; and
compensating the transmitting time of the sync packet, which is received at the sync packet receiving step, on the basis of the delay time of the sync packet obtained at the delay time estimating step, so as to obtain a compensated time, and rewriting and correcting the time of the clock unit with the compensated time.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A printed circuit board having means for protecting electronic components of a circuit carried upon said board from damage due to high electrical transients, said board comprising:
a) a substrate of dielectric material having first and second, planar surfaces;
b) a first, signal carrying area of conductive material on said first surface bounded by a first peripheral edge having a first edge portion;
c) a printed circuit on at least one of said surfaces for connection of said components, said printed circuit being electrically connected to said first area by a first conductive path;
d) a second, grounded area of conductive material on said first surface bounded by a second peripheral edge having a second edge portion; and
e) said first and second edge portions being physically spaced by a distance forming a second conductive path for conducting electrical surges exceeding a predetermined value from said first to second area of conducting material, whereby said surges are shunted from said first conductive path to ground.
2. The circuit board of claim 1 where said first and second edge portions are substantially uniformly spaced along their full lengths.
3. The circuit board of claim 1 wherein the spacing between said first and second edge portions varies along their lengths.
4. The circuit board of claim 3 where said spacing varies between not less than one and not more than ten mils.
5. The circuit board of claim 1 wherein at least one of said first and second edge portions is substantially linear along its entire length.
6. The circuit board of claim 5 wherein both said first and second edge portions are linear along substantially their entire lengths.
7. The circuit board of claim 1 wherein at least one of said first and second edge portions is zig-zag along at least a portion of its length.
8. The circuit board of claim 7 wherein both said first and second edge portions are zigzag along at least a portion of their lengths.
9. The circuit board of claim 8 where both said first and second edge portions are zigzag, and are substantially uniformly spaced, along substantially their entire lengths.