1. A method of making an SOI device with increased channel width in a full-depletion SRAM, comprising the steps of:
applying a first layer of an oxide to an SOI substrate;
applying a first layer of polysilicon to the first layer of oxide;
patterning and etching the first layer of polysilicon to create a first predetermined area substantially corresponding to a SRAM cell area;
patterning and etching the first layer of an oxide to correspond to a logic area;
performing shallow trench silicon RIE at the SRAM cell area;
depositing a first layer of a nitride over the SRAM cell area and the logic area;
performing RIE over the logic area;
depositing a second layer of an oxide over the SRAM cell area and the logic area;
etching back the second layer of an oxide over the SRAM cell area, between a plurality of device areas in the logic area, and between the SRAM cell area and the adjacent device area;
removing the exposed oxide over the SRAM cell area and around the sides of each of the plurality of devices;
performing silicon RIE between the plurality of device areas in the logic area and between the SRAM cell area and the adjacent device area;
depositing a second layer of a nitride over the SRAM cell area and the logic area;
performing a first chemical mechanical polishing step to remove all the deposited films down to about a top edge of the remaining first polysilicon layer;
removing the first polysilicon layer;
removing the exposed silicon oxide layer;
epitaxially growing a first layer of silicon into the voids created by the steps of removing the first polysilicon layer and removing the exposed silicon oxide layer;
performing a second chemical mechanical polishing step to remove all the deposited films down to about the same level as the first chemical mechanical polishing step;
removing the second nitride layer;
depositing a third oxide layer over the SRAM cell area and over a portion of each of the plurality of device areas;
depositing a gate electrode substantially over the third oxide layer;
depositing a spacer layer adjacent the gate electrode and third oxide layer;
depositing a silicide layer on the exposed first epitaxial silicon layer and over a portion of the gate electrode; and
depositing contacts, each of said contacts in electrical connection with one of the silicide layers.
2. A product produced by the method of claim 1.
3. The method of claim 1, wherein the oxide layers are silicon oxides.
4. The method of claim 1, wherein the nitride layers are silicon nitrides.
5. The method of claim 3, wherein the silicon oxide is SiO2.
6. The method of claim 4, wherein the silicon nitride is SiN.
7. A method of making an SOI device with increased channel width in a full-depletion SRAM, comprising the steps of:
applying a first layer of silicon oxide to an SOI substrate;
applying a first layer of polysilicon to the first layer of silicon oxide;
applying a first layer of resist to a first predetermined area of the first layer of polysilicon via masking, the first predetermined area substantially corresponding to a SRAM cell area;
etching the first layer of polysilicon to leave only an area of polysilicon under the first layer of resist;
stripping the first layer of resist;
applying a second layer of resist to a logic area of the first layer of silicon oxide via masking;
performing shallow trench silicon RIE at the SRAM cell area;
stripping the second layer of resist;
depositing a first layer of silicon nitride over the SRAM cell area and the logic area;
applying a third layer of resist over the SRAM cell area and over each of a plurality of device areas in the logic area;
performing silicon nitride RIE over the logic area;
stripping the third layer of resist;
depositing a second layer of silicon oxide over the SRAM cell area and the logic area;
etching back the second layer of silicon oxide over the SRAM cell area, between the plurality of device areas in the logic area, and between the SRAM cell area and the adjacent device area;
applying a fourth layer of resist over a portion of each of the plurality of device areas in the logic area;
removing the exposed oxide over the SRAM cell area and around the sides of each of the plurality of devices not covered by resist;
stripping the fourth layer of resist;
performing silicon RIE between the plurality of device areas in the logic area and between the SRAM cell area and the adjacent device area;
depositing a second layer of silicon nitride over the SRAM cell area and the logic area;
performing a first chemical mechanical polishing step to remove all the deposited films down to about a top edge of the remaining first polysilicon layer;
removing the first polysilicon layer;
removing the exposed silicon oxide layer;
epitaxially growing a first layer of silicon into the voids created by the steps of removing the first polysilicon layer and removing the exposed silicon oxide layer;
performing a second chemical mechanical polishing step to remove all the deposited films down to about the same level as the first chemical mechanical polishing step;
removing the second silicon nitride layer;
depositing a third silicon oxide layer over the SRAM cell area and over a portion of each of the plurality of device areas;
depositing a gate electrode substantially over the third silicon oxide layer;
depositing a spacer layer adjacent the gate electrode and third silicon oxide layer;
depositing a silicide layer on the exposed first epitaxial silicon layer and over a portion of the gate electrode; and
depositing contacts, each of said contacts in electrical connection with one of the silicide layers.
8. The method of claim 1, wherein the applying a fourth layer of resist is accomplished via shallow trench patterning.
9. The method of claim 1, wherein the removing the first polysilicon layer includes removing via RIE or wet etching.
10. The method of claim 1, wherein the removing the exposed silicon oxide layer includes removing via wet etching.
11. A product produced by the method of claim 1.
12. An SOI device with increased channel width, comprising:
a FET including:
a drain contact electrode and a source contact electrode;
a gate electrode deposited over a layer of epitaxial silicon, the epitaxial silicon forming a sidewall that extends the width of the FET.
13. The device of claim 12, further comprising a spacer layer between the gate electrode and each of the drain and source contact electrodes.
14. The device of claim 12, wherein the FET is a fully-depleted FET.
15. A method of making an SOI device with increased channel width, comprising:
depositing a layer of epitaxial silicon on a silicon substrate, the silicon substrate having an oxide layer buried within;
depositing a gate electrode over the layer of epitaxial silicon;
depositing source and drain contact electrodes, the source and drain contact electrodes electrically coupled to silicide layers and disposed on opposing sides of the gate electrode.
16. The method of claim 15, wherein the source and drain contact electrodes are separated from the gate electrode by a spacer layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A motor-noise absorbing apparatus for absorbing noise generated in a motor housing, comprising:
a body configured to be seated and fixed on a peripheral part of an opening of the motor housing to to restrict an amount of air discharged between the motor housing and a stator core;
a first air discharging part formed in the middle of the body, so that most of the air is discharged between the stator core and a rotor; and
at least one second air discharging part formed to penetrate a peripheral part of the body, so that a portion of the air is discharged between the motor housing and the stator core.
2. The apparatus as claimed in claim 1, wherein the second air discharging part is formed in an area smaller than that of the first air discharging part, so that the amount of the air discharged between the motor housing and the stator core is less than that of the air discharged between the stator core and the rotor.
3. The apparatus as claimed in claim 2, wherein the second air discharging part comprises at least one grill-shaped part.
4. The apparatus as claimed in claim 2, wherein the second air discharging part comprises at least one porous part in which a plurality of small holes is formed.
5. The apparatus as claimed in claim 2, wherein the second air discharging part comprises at least two elongated holes disposed symmetrical to each other about the first air discharging part.
6. The apparatus as claimed in claim 2, wherein the second air discharging part comprises at least four elongated holes disposed symmetrical to one another about the first air discharging part.
7. The apparatus as claimed in claim 1, wherein the body is configured, so that an upper surface thereof is increasingly rounded in an inward-and-down direction toward a center side from a peripheral side, thereby smoothly discharging the most of the air between the stator core and the rotor.
8. A vacuum cleaner motor comprising:
a motor housing having a flange;
a stator core disposed in the motor housing;
a rotor disposed in the stator core so that a first space is defined between the stator core and the rotor, the stator core disposed in the motor housing so that a second space is defined between the motor housing and the stator core;
a motor housing cover; and
a motor-noise absorbing apparatus disposed between the flange and the motor housing cover, the motor-noise absorbing apparatus comprising a first air discharging part and at least one second air discharging part, the first and second air discharging parts configured so that an amount of air discharged through the second space is less than an amount of air discharged through the first space.
9. The motor as claimed in claim 8, wherein the second air discharging part is formed in an area smaller than that of the first air discharging part.
10. The motor as claimed in claim 8, wherein the second air discharging part comprises at least one grill-shaped part.
11. The motor as claimed in claim 8, wherein the second air discharging part comprises at least one porous part in which a plurality of small holes is formed.
12. The motor as claimed in claim 8, wherein the second air discharging part comprises at least two elongated holes disposed symmetrical to each other about the first air discharging part.
13. The motor as claimed in claim 8, wherein the second air discharging part comprises at least four elongated holes disposed symmetrical to one another about the first air discharging part.