I claim:
1. An electrical harness which is suitable for use in an automatic transmission and which, when it is so used, is at least partially immersed in automatic transmission fluid;
said harness comprising
(1) a plurality of electrical connectors, and
(2) a plurality of insulated wires, at least some of the insulated wires being physically and electrically connected to the connectors, and at least some of the insulated wires comprising (a) a wire, and (b) an electrically insulating jacket which surrounds the wire and is composed of an insulating polymeric composition comprising a polymeric component which comprises at least 50% by weight, based on the weight of the polymeric component, of a block copolymer which comprises
(i) first polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride, and
(ii) second polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride and at least one other fluorine-containing comonomer, and in which the repeating units are randomly copolymerize;
the ratio by weight of the units derived from vinylidene fluoride in the first blocks to the units derived from vinylidene fluoride in the second blocks being from 40:60 to 95:5, and the block copolymer containing 0.5 to 30% by weight of units derived from the other fluorine-containing comonomer.
2. A harness according to claim 1 wherein the polymeric component consists essentially of the block copolymer, and the block copolymer consists essentially of said first and second polymeric blocks.
3. A harness according to claim 1 wherein the block copolymer has been prepared by a process which comprises
(A) preparing a reactive oligomer corresponding to the first blocks by polymerizing a first monomer component which comprises at least 95% by weight vinylidene fluoride, and
(B) adding to the reaction mixture from step (1) a second monomer component which comprises vinylidene fluoride and at least one fluorine-containing comonomer, and copolymerizing the second monomer component on the reactive oligomer, thereby preparing the block copolymer.
4. A harness according to claim 3 wherein the polymerization steps (A) and (B) are carried out by emulsion polymerization.
5. A harness according to claim 3 wherein the polymerization steps (A) and (B) are carried out by suspension polymerization.
6. A harness according to claim 1 wherein the block copolymer has a melting point of at least 160 C.
7. A harness according to claim 1 wherein (a) the first blocks consist essentially of units derived from vinylidene fluoride and (b) the other fluorine-containing monomer in the second polymeric blocks is at least one monomer selected from the group consisting of fluoroalkenes, fluoroalkoxyalkenes, and fluoroalkylvinyl ethers.
8. A harness according to claim 1 wherein the other fluorine-containing monomer in the second polymeric blocks is at least one monomer selected from the group consisting of hexafluoropropylene, tetrafluoroethylene, chlorotrifluoroethylene, perfluoroethoxyethylene, perfluoropropylvinyl ether, perfluoromethylvinyl ether, perfluoroethylvinyl ether and perfluorobutylvinyl ether.
9. A harness according to claim 1 wherein (a) the first blocks consist essentially of units derived from polyvinylidene fluoride and (b) the other fluorine-containing monomer in the second polymeric blocks consists essentially of hexafluoropropylene, and the block copolymer contains 5 to 15% by weight of units derived from hexafluoropropylene.
10. A harness according to claim 1 wherein said insulating jacket is the only insulating jacket around at least some of the wires, and the thickness of the insulating jacket is 0.005 to 0.025 inch.
11. A harness according to claim 1 wherein said insulating jacket contacts the conductor and is 0.002 to 0.005 inch thick, and is surrounded by a second insulating jacket which is 0.008 to 0.020 inch thick.
12. A harness according to claim 1 wherein at least one of the wires is a stranded wire containing a blocking compound between the strands of the wire.
13. A harness according to claim 1 wherein the polymeric composition contains at least 75% by weight, based on the weight of the composition, of the block copolymer.
14. An electrical harness which is suitable for use in an automatic transmission in an automobile and which, when it is so used, is at least partially immersed in automatic transmission fluid and forms part of an electrical circuit which is powered by a battery;
said harness comprising
(1) a plurality of electrical connectors, and
(2) a plurality of insulated wires, at least some of the insulated wires being physically and electrically connected to the connectors, and each of the insulated wires comprising (a) a stranded wire and (b) an electrically insulating jacket which surrounds the wire and is composed of an insulating polymeric composition comprising at least 50% by weight, based on the weight of the composition, of a block copolymer which consists essentially of
(i) first polymeric blocks which consist essentially of repeating units derived from vinylidene fluoride, and
(ii) second polymeric blocks which consist essentially of repeating units derived from vinylidene fluoride and from at least one other fluorine-containing comonomer selected from hexafluoropropylene, tetrafluoroethylene, and chlorotrifluoroethylene, and in which the repeating units are randomly copolymerized;
the ratio by weight of the units derived from vinylidene fluoride in the first blocks to the units derived from vinylidene fluoride in the second blocks being from 65:35 to 85:15, and the block copolymer containing 5 to 15% by weight of units derived from the other fluorine-containing comonomer.
15. A harness according to claim 14 wherein said insulating jacket is the sole insulation around each of the wires and is 0.006 to 0.015 inch thick.
16. A harness according to claim 15 wherein the block copolymer is crosslinked.
17. Apparatus which comprises
(1) a casing which is suitable for use as part of an automatic transmission and which contains an automatic transmission fluid when it is so used, and
(2) an insulated wire which is physically attached to the casing but electrically insulated therefrom at the point of physical attachment, and which, when the casing is in use as part of an automatic transmission and contains an automatic transmission fluid,
(a) is at least partially immersed in the automatic transmission fluid,
(b) forms part of an electrical circuit which is powered by direct current, and
(c) comprises a wire, and an electrically insulating jacket which surrounds the wire and is composed of an insulating polymeric composition comprising a polymeric component which comprises at least 50% by weight, based on the weight of the polymeric component, of a block copolymer which comprises
(i) first polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride, and
(ii) second polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride and at least one other fluorine-containing comonomer, and in which the repeating units are randomly copolymerized;
the ratio by weight of the units derived from vinylidene fluoride in the first blocks to the units derived from vinylidene fluoride in the second blocks being from 40:60 to 95:5, and the block copolymer containing 0.5 to 30% by weight of units derived from the other fluorine-containing comonomer.
18. Apparatus according to claim 17 wherein the insulating polymeric composition contains at least 80% by weight of the block copolymer; the block copolymer consists essentially of said first and second polymeric blocks and has a melting point of at least 163 C.; the first blocks consist essentially of units derived from vinylidene fluoride, and the second blocks consist essentially of units derived from vinylidene fluoride and another fluorine-containing monomer selected from the group consisting of hexafluoropropylene, tetrafluoroethylene, and chlorotrifluoroethylene; the ratio by weight of the units derived from vinylidene fluoride in the first blocks to the units derived from vinylidene fluoride in the second blocks is from 70:30 to 80:20, and the block copolymer contains 5 to 15% by weight of units derived from the other fluorine-containing comonomer.
19. Apparatus according to claim 18 wherein said insulating jacket is the only insulating jacket around the wire and is 0.006 to 0.015 inch thick.
20. An automatic transmission which is part of a road vehicle and which includes
(1) a casing which contains an automatic transmission fluid, and
(2) an insulated wire which
(a) is at least partially immersed in the automatic transmission fluid,
(b) forms part of an electrical circuit which is powered by a battery, and
(c) comprises a wire, and an electrically insulating jacket which surrounds the wire and is contacted by the transmission fluid, the insulating jacket being composed of an insulating polymeric composition comprising a polymeric component which comprises at least 50% by weight, based on the weight of the polymeric component, of a block copolymer which comprises
(i) first polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride, and
(ii) second polymeric blocks in which at least 95% by weight of the repeating units are derived from vinylidene fluoride and at least one other fluorine-containing comonomer, and in which the repeating units are randomly copolymerized;
the ratio by weight of the units derived from vinylidene fluoride in the first blocks to the units derived from vinylidene fluoride in the second blocks being from 40:60 to 95:5, and the block copolymer containing 0.5 to 30% by weight of units derived from the other fluorine-containing comonomer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for switching packet data associated with a network, the system comprising:
a memory array;
a plurality of input and output ports to be coupled to a network device;
a plurality of serial registers each associated with a different one of the plurality of input ports, each of the serial registers further being segmented into a plurality of segments, each of the serial registers configured for receiving packet data from the associated input port at a first segment of the serial register concurrent with writing other packet data to the memory array from a second segment of the serial register, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array;
a switching circuit configured to route received packet data to at least one of the plurality of output ports according to a subset of the packet data;
at least one media access controller (MAC) configured to transmit and receive the packet data at least one of the plurality of input and output ports;
a plurality of command control units each for receiving a command that indicates a selected operation to be performed;
a memory management device for determining a location in the memory array where the packet data is to be written, that determination being made in response to a command that indicates that a write operation is to be performed;
a packet table that stores a pointer to the location in the memory array determined by the memory management device; and
an input queue having a pointer structure,
wherein each of said plurality of command control units is associated with one or more input and output ports, the commands received by a given command control unit indicating desired operations to be performed on packet data that is associated with the associated ports such that commands are distributed across the plurality of command control units,
wherein said memory management device receives an indication of an input queue for storing packet data received by an input port before an associated write command is received by the associated command control unit, said write command including the indication of the input queue that the packet data should be stored in.
2. The system described in claim 1, wherein the memory management device is incorporated on the same semiconductor chip as the memory array.
3. The system described in claim 1, wherein the indication of the input queue is a queue identifier that references the input queue independently from a physical location in the memory array where the packet data is stored.
4. The system described in claim 3, wherein a read command that is issued to a command control unit causes the memory management device to responsively move a pointer that indicates a desired packet data to be read, to an associated output queue.
5. The system described in claim 4, wherein each of said input ports comprises:
a data signal for conveying a serial stream of packet data between the input port and an associated one of the serial registers;
a clock signal that oscillates at a frequency to which said data signal is synchronized; and
a mask signal that is asserted or de-asserted to qualify the meaning of said serial stream of data, said qualification indicating a valid logic level of said serial data, whether said serial data is invalid or whether the end of a packet that comprises said serial stream of data has been reached.
6. The system described in claim 5, wherein each element of said serial stream of packet data is asserted on a rising edge of said clock signal.
7. The system described in claim 5, wherein each element of said serial stream of packet data is asserted on the rising and falling edges of said clock signal.
8. The system described in claim 1, wherein the plurality of input and output ports is a plurality of bidirectional inputoutput ports.
9. The system described in claim 1, wherein the subset of the packet data includes a header of the packet data.
10. A system for switching packet data associated with a network, the system comprising:
a memory array;
a plurality of input and output ports to be coupled to a network device;
a plurality of serial registers each associated with a different one of the plurality of input ports, each of the serial registers further being segmented into a plurality of segments, each of the serial registers configured for receiving packet data from the associated input port at a first segment of the serial register concurrent with writing other packet data to the memory array from a second segment of the serial register, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array;
a switching circuit configured to route received packet data to at least one of the plurality of output ports according to a subset of the packet data;
at least one media access controller (MAC) configured to transmit and receive the packet data at least one of the plurality of input and output ports;
a plurality of command control units each for receiving a command that indicates a selected operation to be performed;
a memory management device for determining a location in the memory array where the packet data is to be written, that determination being made in response to a command that indicates that a write operation is to be performed;
a packet table that stores a pointer to the location in the memory array determined by the memory management device; and
an input queue having a pointer structure,
wherein each of said plurality of command control units is associated with one or more input and output ports, the commands received by a given command control unit indicating desired operations to be performed on packet data that is associated with the associated ports such that commands are distributed across the plurality of command control units, and
wherein said plurality of command control units are each coupled to a command bus for conveying said commands from said network controller device, said commands being variable length byte streams wherein each element of said variable length byte streams are asserted on a selected edge of a command clock signal that is also coupled to said command control units.
11. The system described in claim 10, wherein the plurality of input and output ports is a plurality of bidirectional inputoutput ports.
12. The system described in claim 10, wherein the subset of the packet data includes a header of the packet data.
13. A system for switching packet data associated with a network, the system comprising:
a memory array;
a plurality of input and output ports to be coupled to a network device;
a plurality of serial registers each associated with a different one of the plurality of input ports, each of the serial registers further being segmented into a plurality of segments, each of the serial registers configured for receiving packet data from the associated input port at a first segment of the serial register concurrent with writing other packet data to the memory array from a second segment of the serial register, segments of respective serial registers being associated with corresponding portions of the memory array, segments of different serial registers simultaneously transferring packet data to different portions of the memory array;
a switching circuit configured to route received packet data to at least one of the plurality of output ports according to a subset of the packet data;
at least one media access controller (MAC) configured to transmit and receive the packet data at least one of the plurality of input and output ports;
a plurality of command control units each for receiving a command that indicates a selected operation to be performed;
a memory management device for determining a location in the memory array where the packet data is to be written, that determination being made in response to a command that indicates that a write operation is to be performed;
a packet table that stores a pointer to the location in the memory array determined by the memory management device; and
an input queue having a pointer structure,
wherein each of said plurality of command control units is associated with one or more input and output ports, the commands received by a given command control unit indicating desired operations to be performed on packet data that is associated with the associated ports such that commands are distributed across the plurality of command control units, and
wherein each of a plurality of command flag signals are coupled to different ones of said command control, said command flag signals being de-asserted when an associated one of said commands is conveyed on said command bus and said command flag signals being asserted when an end of said associated one of said commands has been reached.
14. The system described in claim 13, further comprising a programmable delay-lock loop for adjusting a phase difference between an edge of a QSCAL signal and an edge of a QS signal, said phase difference being adjusted in response to a timing reference command issued on a given command bus that is associated therewith.
15. The system described in claim 13, wherein the plurality of input and output ports is a plurality of bidirectional inputoutput ports.
16. The system described in claim 13, wherein the subset of the packet data includes a header of the packet data.