1. A ring-shaped resistance heater for supplying heat to a growing single crystal, comprising:
an upper and a lower ring, which are electrically conductively connected by means of a loop adjacent to a ring gap of the lower ring, such that the flow direction of electric current which is conducted through the rings is opposite in the rings;
connecting elements which hold the upper and lower rings together in a spaced apart relationship; and
current leads for conducting electric current through the upper and lower rings.
2. The resistance heater of claim 1, wherein the upper and lower rings and the current leads consist predominantly of carbon.
3. The resistance heater of claim 1, wherein edges of the upper and lower rings are rounded.
4. The resistance heater of claim 2, wherein edges of the upper and lower rings are rounded.
5. The resistance heater of claim 1, wherein the connecting elements each comprise a ring-shaped spacer, hollow cylinders, a screw and a screw nut, wherein the ring-shaped spacer is arranged between the rings, the hollow cylinders line holes through the rings in the thickness direction, and the screw is screwed at its end to the screw nut and extends through the hollow cylinders and the spacer.
6. The resistance heater of claim 4, wherein collars of the hollow cylinders are countersunk in side areas of the upper and lower rings.
7. The resistance heater of claim 1, wherein the upper and lower rings are held together by connecting elements at a location which lies alongside the loop and alongside the current lead of the lower ring.
8. The resistance heater as claimed in any of claims 1 to 6, wherein the upper ring is fixed to the current lead of the upper ring by means of a screw composed of graphite.
9. The resistance heater of claim 1, wherein the lower ring is fixed to the current lead of the lower ring by means of a screw comprising CFC.
10. The resistance heater of claim 1, wherein a clamping connection that secures the current leads against an electromagnetic force compressing them is mounted in the current leads.
11. The resistance heater of claim 10, wherein the clamping connection comprises a pin, which is arranged transversally with respect to the longitudinal direction of the current leads and over which electrically insulating mounts are slipped, and a screw, which holds the mounts and the pin in position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory array, comprising:
a plurality fins protruding from a substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein each fin comprises an upper surface rounded by isotropic etching.
2. The memory array of claim 1, wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.
3. The memory array of claim 1, wherein each floating gate overlies a portion of its corresponding fin that protrudes from the substrate.
4. The memory array of claim 3, wherein each floating gate that overlies a portion of its corresponding fin that protrudes from the substrate terminates at a location that coincides with an axis that bisects a width of that corresponding fin.
5. The memory array of claim 3, wherein each floating gate that overlies a portion of its corresponding fin that protrudes from the substrate extends past a location that coincides with an axis that bisects a width of that corresponding fin.
6. A memory array, comprising:
a plurality of isolation regions extending into a substrate;
a plurality fins protruding from the substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein an isolation region is located between successive fins; and
wherein at least one fin is in contact with an isolation region.
7. A memory array, comprising:
a plurality fins protruding from a substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.
8. A memory array, comprising:
a substrate;
a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;
a fin protruding from each active region;
a floating gate memory cell formed on each active region, the memory cell comprising:
a tunnel dielectric layer formed on the active region, including the fin of that active region;
a floating gate formed on a portion of the tunnel dielectric layer;
an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and
a control gate layer formed on the intergate dielectric layer.
9. The memory array of claim 8, wherein the portion of the floating gate terminates at a location coinciding with an axis that bisects a width of the fin.
10. The memory array of claim 8, wherein the portion of the floating gate overlies about half of the fin.
11. The memory array of claim 8, wherein the portion of the floating gate extends beyond a location coinciding with an axis that bisects a width of the fin.
12. The memory array of claim 8, wherein the portion of the floating gate overlies more than half of the fin.
13. A memory array, comprising:
a plurality of rows of memory cells, each row comprising:
a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;
a fin protruding from each active region;
a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising:
a tunnel dielectric layer formed on the active region, including the fin of that active region;
a floating gate formed on a portion of the tunnel dielectric layer;
an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and
a control gate layer formed on the intergate dielectric layer;
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.
14. The memory array of claim 13, wherein the portion of each floating gate terminates at a location coinciding with an axis that bisects a width of a corresponding fin.
15. The memory array of claim 13, wherein the portion of each floating gate overlies about half of a corresponding fin.
16. The memory array of claim 13, wherein the portion of each floating gate extends beyond a location coinciding with an axis that bisects a width of a corresponding fin.
17. The memory array of claim 13, wherein the portion of each floating gate overlies more than half of a corresponding fin.
18. A memory device, comprising:
a memory array; and
control circuitry for controlling operations of the memory array;
wherein the memory array comprises:
a plurality fins protruding from a substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein each fin comprises an upper surface rounded by isotropic etching.
19. A memory device, comprising:
a memory array; and
control circuitry for controlling operations of the memory array;
wherein the memory array comprises:
a plurality of isolation regions extending into a substrate;
a plurality fins protruding from the substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein an isolation region is located between successive fins; and
wherein at least one fin is in contact with an isolation region.
20. A memory device, comprising:
a memory array; and
control circuitry for controlling operations of the memory array;
wherein the memory array comprises:
a substrate;
a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;
a fin protruding from each active region;
a floating gate memory cell formed on each active region, the memory cell comprising:
a tunnel dielectric layer formed on the active region, including the fin of that active region;
a floating gate formed on a portion of the tunnel dielectric layer;
an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and
a control gate layer formed on the intergate dielectric layer.
21. A memory device, comprising:
a memory array; and
control circuitry for controlling operations of the memory array;
wherein the memory array comprises:
a plurality fins protruding from a substrate;
a tunnel dielectric layer overlying the fins;
a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;
an intergate dielectric layer overlying the floating gates; and
a control gate layer overlying the intergate dielectric layer;
wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.
22. A memory device, comprising:
a memory array; and
control circuitry for controlling operations of the memory array;
wherein the memory array comprises:
a plurality of rows of memory cells, each row comprising:
a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;
a fin protruding from each active region;
a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising:
a tunnel dielectric layer formed on the active region, including the fin of that active region;
a floating gate formed on a portion of the tunnel dielectric layer;
an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and
a control gate layer formed on the intergate dielectric layer;
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.
23. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises a memory array, comprising:
a plurality of rows of memory cells, each row comprising:
a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;
a fin protruding from each active region;
a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising:
a tunnel dielectric layer formed on the active region, including the fin of that active region;
a floating gate formed on a portion of the tunnel dielectric layer;
an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and
a control gate layer formed on the intergate dielectric layer;
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and
wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.