1. A method of cleaning a substrate having a plurality of high-aspect ratio openings, the method comprising:
providing a substrate having a plurality of high-aspect ratio openings into a plasma processing chamber, each of the openings having a height to lateral dimension aspect ratio of greater than about 10:1;
flowing a first etchant including a fluorine-based species towards the substrate;
applying a first bias power to the plasma processing chamber to generate a plasma of the fluorine-based species to remove silicon oxide in the high-aspect ratio openings;
flowing a second etchant including a hydrogen-based species towards the substrate; and
applying a source power and a second bias power to the plasma processing chamber to generate a plasma of the hydrogen-based species to remove silicon in the high-aspect ratio openings.
2. The method of claim 1, wherein the second etchant consists only of hydrogen.
3. The method of claim 1, wherein the second etchant includes hydrogen and nitrogen trifluoride, a concentration of the hydrogen being greater than a concentration of the nitrogen trifluoride.
4. The method of claim 1, wherein the first etchant consists only of nitrogen trifluoride.
5. The method of claim 1, wherein the removal of the silicon oxide occurs without any source power being applied in the plasma processing chamber.
6. The method of claim 1, wherein the substrate includes a plurality of vertical structures defining each of the high-aspect ratio openings, each of the vertical structures including alternating layers of oxide and nitride.
7. The method of claim 6, wherein the alternating layers of oxide and nitride include alternating layers of silicon oxide and silicon nitride.
8. The method of claim 6, wherein removal of the silicon in the high aspect ratio openings occurs at a selectivity greater than about 500:1 over each of the alternating layers of oxide and nitride.
9. The method of claim 1, wherein a pressure in the plasma processing chamber is less than about 10 mTorr while flowing the first etchant towards the substrate and applying the first bias power.
10. The method of claim 1, wherein a ratio between the source power and the second bias power to remove the silicon is about equal to or greater than about 2:1.
11. The method of claim 1, wherein the silicon includes amorphous or damaged silicon.
12. The method of claim 1, wherein the source power is applied to a remote plasma source in the plasma processing chamber, and wherein applying the source power includes exposing the hydrogen-based species to the remote plasma source to generate radicals of the hydrogen-based species.
13. The method of claim 1, wherein applying the first bias power includes exposing the fluorine-based species to the first bias power to generate ions of the fluorine-based species.
14. The method of claim 1, wherein the plurality of high-aspect ratio openings are part of a vertical NAND structure.
15. An apparatus for cleaning a substrate having a plurality of high-aspect ratio openings, the apparatus comprising:
a plasma processing chamber, wherein the plasma processing chamber includes:
a remote plasma source; and
a substrate support for supporting a substrate having a plurality of high-aspect ratio openings, each of the openings having a height to lateral dimension aspect ratio of greater than about 10:1, and the substrate having a silicon oxide layer over a silicon layer in the high-aspect ratio openings; and
a controller configured to provide instructions for performing the following operations:
(a) flowing a first etchant including a fluorine-based species towards the substrate;
(b) applying a first bias power to the substrate support in the plasma processing chamber to generate a plasma of the fluorine-based species to remove the silicon oxide layer;
(c) flowing a second etchant including a hydrogen-based species towards the substrate; and
(d) applying a source power to the remote plasma source and a second bias power to the substrate support in the plasma processing chamber to generate a plasma of the hydrogen-based species to remove the silicon layer.
16. The apparatus of claim 15, wherein the second etchant consists only of hydrogen.
17. The apparatus of claim 15, wherein the second etchant includes hydrogen and nitrogen trifluoride, a concentration of the hydrogen being greater than a concentration of the nitrogen trifluoride.
18. The apparatus of claim 15, wherein the first consists only of nitrogen trifluoride.
19. The apparatus of claim 15, wherein the substrate includes a plurality of vertical structures defining each of the high-aspect ratio openings, each of the vertical structures including alternating layers of oxide and nitride.
20. The apparatus of claim 19, wherein the removal of the silicon layer occurs at a selectivity greater than about 500:1 over each of the alternating layers of oxide and nitride.
21. The apparatus of claim 15, wherein a pressure in the plasma processing chamber is less than about 10 mTorr while flowing the first etchant towards the substrate and applying the first bias power.
22. The apparatus of claim 15, wherein a ratio between the source power and the second bias power to remove the silicon layer is about equal to or greater than about 2:1.
23. A method of cleaning a substrate having a plurality of high-aspect ratio openings, the method comprising:
providing a substrate having a plurality of high-aspect ratio openings into a plasma processing chamber, each of the openings having a height to lateral dimension aspect ratio of greater than about 10:1;
flowing a first etchant including a fluorine-based species or a hydrogen-based species towards the substrate;
applying a first bias power to the plasma processing chamber to generate a plasma of the first etchant to remove silicon oxide in the high-aspect ratio openings;
flowing a second etchant including a hydrogen-based species towards the substrate; and
applying a source power and a second bias power to the plasma processing chamber to generate a plasma of the second etchant to remove silicon in the high-aspect ratio openings.
24. The method of claim 23, wherein the first etchant includes the hydrogen-based species, and wherein the removed silicon oxide includes removed native silicon oxide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power management system of a digital signal processor, the system comprising:
a command decoding device for decoding a program into which a PSM (Power Saving Mode) command and a general command are inserted and transmitting module information required for execution of a corresponding command to a power management control apparatus at the time of decoding the corresponding command;
a pipeline control device for blocking and restarting transmission of data through a pipeline upon receipt of a pipeline control signal (pipeline stall) from the power management control apparatus; and
the power management control apparatus for controlling power in respective modules by settingresetting corresponding bits of a PSM status register and a PSM flag register in accordance with the PSM command and the general command decoded in the command decoding device.
2. The system of claim 1, wherein the power management control apparatus setsresets bits of a corresponding module in the PSM status register upon receipt of the PSM command decoded in the command decoding device and setting bits of a corresponding module in the PSM flag register upon receipt of module information required to execute a general command from the command decoding device to control power supply to the corresponding module depending on the status of the bits of the corresponding module of the PSM status register and the PSM flag register.
3. The system of claim 2, wherein the power management control apparatus controls power supply to the corresponding module depending on the status of the bits of the corresponding module of the PSM status register and the PSM flag register,
wherein if the bits of the corresponding module of the PSM status register are set, the bits of the corresponding module of the PSM flag register are set to control power supply to the corresponding module, and if the bits of the corresponding module of the PSM status register are not set, the bits of the corresponding module are set in the PSM flag register and a pipeline control signal (pipeline stall) is transmitted to the pipeline control device to stop the execution of a pipeline and then the bits of the corresponding module are set in the PSM status register to control power supply to the corresponding module.
4. The system of claim 1, wherein upon receipt of an external control signal PSM_EN capable of enablingdisabling the execution of a PSM command from the outside of the digital signal processor, the command decoding device executes the PSM command if the external control signal is a control signal enabling the execution of the PSM command, and the command decoding device ignores the PSM command if the external control signal is a control signal disabling the execution of the PSM command.
5. The system of claim 1, wherein the PSM command is inserted into a program based on result of simulation.
6. The system of claim 1, wherein the PSM command is inserted into a program based on result of simulation and power profiling of the program.
7. A power management method of a digital signal processor, the method comprising the steps of:
a) upon receipt of a PSM command, settingresetting bits of a corresponding module in a PSM status register in accordance with the PSM command;
b) setting bits of a corresponding module in a PSM flag register upon receipt of module information required to execute a general command; and
c) controlling power in respective modules depending on the status of the bits of the corresponding module of the PSM status register and the PSM flag register.
8. The method of claim 7, wherein the step c) of controlling power includes the steps of:
c1) checking the bits of the corresponding module in the PSM status register;
c2) executing the general command if the bits of the corresponding module are set as the result of the checking; and
c3) if the bits of the corresponding module are not set as the result of the checking, setting the bits of the corresponding module in the PSM flag register to stop the execution of a pipeline by using a pipeline control signal (pipeline stall), and then setting the bits of the corresponding module in the PSM status register to control power supply to the corresponding module.
9. The method of claim 7, wherein a decoding process is performed for decoding the general command, and the module information is received in the decoding process so that the module information can be processed immediately without time delay upon input of the corresponding general command to a power management unit.
10. The method of claim 9, wherein the PSM command is inserted into a program based on result of simulation.
11. The method of claim 9, wherein the PSM command is inserted into a program based on result of simulation and power profiling of the program.
12. A power management control apparatus of a digital signal processor, the apparatus comprising:
a PSM status register for storing bits of a corresponding module in accordance with a PSM command;
a PSM flag register for storing bits of a corresponding module in accordance with a general command; and
a power management controller for settingresetting bits of the PSM status register and the PSM flag register in accordance with a PSM command and a general command decoded by an external command decoding device to control power in respective modules.
13. The apparatus of claim 12, wherein the PSM command is inserted into a program based on result of simulation.
14. The apparatus of claim 12, wherein the PSM command is inserted into a program based on result of simulation and power profiling of the program.