1. A vibration acceleration sensor, comprising:
an oscillator unit for outputting an oscillator signal, the oscillator unit including:
a first piezoelectric vibrating reed having a vibrating arm that performs bending vibration; and
an oscillator circuit for oscillating the first piezoelectric vibrating reed;
a phase shifting unit for shifting and outputting a given phase angle of an output signal of the oscillator unit;
a phase shift circuit unit provided with a second piezoelectric vibrating reed having a vibrating arm that performs bending vibration, arranged at an output side of the phase shifting unit;
a multiplier for multiplying an output signal of the phase shift circuit unit by the output signal of the oscillator circuit; and
a phase shift modification output unit which receives an output from the multiplier and outputs a value corresponding to a change in a phase shift angle of an input-output signal of the phase shift circuit unit;
a resonant frequency of the second piezoelectric vibrating reed being equal to a frequency of the output signal of the oscillator unit, in a state where no acceleration is applied.
2. The vibration acceleration sensor according to claim 1, wherein the first piezoelectric vibrating reed and the second piezoelectric vibrating reed are arranged so that an axis direction of the vibrating arm of the first piezoelectric vibrating reed and an axis direction of the vibrating arm of the second piezoelectric vibrating reed are opposite from each other.
3. The vibration acceleration sensor according to claim 1, wherein a frequency-phase shift characteristic of the phase shift circuit unit is point symmetric with respect to the resonant frequency of the second piezoelectric vibrating reed without acceleration.
4. The vibration acceleration sensor according to claim 1, wherein the first piezoelectric vibrating reed and the second piezoelectric vibrating reed are tuning fork vibrating reeds formed with a piezoelectric material.
5. The vibration acceleration sensor according to claim 1, wherein the first piezoelectric vibrating reed and the second piezoelectric vibrating reed are double-ended tuning fork vibrating reeds formed with a piezoelectric material.
6. The vibration acceleration sensor according to claim 1, further comprising:
a package accommodating the first piezoelectric vibrating reed and an integrated circuit, both forming the oscillator circuit, and the second piezoelectric vibrating reed included in a phase-shift circuit unit; and
a lid sealing the package in an air tight manner.
7. The vibration acceleration sensor according to claim 6, wherein the package is formed having two cavities stacked one on top of the other, each cavity including an interconnection substrate, one cavity accommodating the first and the second piezoelectric vibrating reeds, and the other cavity accommodating the integrated circuit.
8. The vibration acceleration sensor according to claim 6, wherein the package is formed having two cavities stacked one on top of the other, having a shared interconnection substrate therebetween, one cavity accommodating the first and the second piezoelectric vibrating reeds, and the other cavity accommodating the integrated circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor storage device comprising:
a plurality of bit-line pairs extending in a first direction;
a first word line extending in a second direction that intersects the first direction;
a first plurality of memory cells provided at intersection points formed by the plurality of bit-line pairs and the first word line;
a plurality of P well areas extending in the first direction;
a plurality of N well areas extending in the first direction;
a plurality of P areas for well tap that are P type, and that have impurity concentration higher than that of the P well areas, said plurality of P areas for well tap being used to supply well potential to the plurality of P well areas; and
a plurality of N areas for well tap that are N type, and that have impurity concentration higher than that of the N well areas, said plurality of N areas for well tap being used to supply well potential to the plurality of N well areas; wherein:
each of the first plurality of memory cells includes first and second PMOS transistors, and first, second, third, and fourth NMOS transistors, said first and second NMOS transistors are formed in one of the plurality of P well areas, said third and fourth NMOS transistors are formed in another one of the plurality of P well areas, said first and second PMOS transistors are formed in one of the plurality of N well areas, said one of the plurality of N well areas is located between said one of the plurality of P well areas and said another one of plurality of P well areas,
among the first plurality of memory cells, different addresses are assigned to first memory cells that are adjacent to each other in the second direction, and
a P well supply line for supplying power to the plurality of P areas for well tap and a N well tap supply line for supplying power to the plurality of N areas for well tap extend in the second direction.
2. The semiconductor storage device according to claim 1, wherein:
the first memory cells which are adjacent to each other in the second direction share a sense amplifier.