1. A radiation imaging device comprising:
a radiation detector for detecting radiation transmitted through an object to be examined, said radiation detector having a scintillator and a detection panel, said scintillator converting said radiation incident upon an incident surface into visible light, said detection panel having a detection surface having a two-dimensional array of pixels each for converting said visible light emitted from said scintillator into an electric signal, said detection surface being opposed to said incident surface of said scintillator;
a housing having a top plate in an irradiation surface irradiated with said radiation, said housing contains said radiation detector in such a position that said detection panel is faced to said top plate; and
an anisotropic heat transfer plate disposed between said top plate and said detection panel in said housing so as to make tightly contact with both said top plate and said detection panel, for transferring heat in a specific first direction.
2. The radiation imaging device according to claim 1, wherein said first direction of said anisotropic heat transfer plate differs from an extending direction of a signal line for reading out said electric signal from said pixels of said detection panel.
3. The radiation imaging device according to claim 1, wherein said anisotropic heat transfer plate has a plurality of carbon fibers oriented in one direction, and said first direction of said anisotropic heat transfer plate coincides with an orientation of said carbon fibers.
4. The radiation imaging device according to claim 1, wherein
each of said top plate and said anisotropic heat transfer plate is formed of a lamination of prepregs, and each of said prepregs is made of carbon fibers oriented in one direction and impregnated with resin;
in said anisotropic heat transfer plate, said orientation of said carbon fibers of all said prepregs are substantially same, and said first direction of said anisotropic heat transfer plate coincides with said orientation of said carbon fibers;
in said top plate, said orientation of said carbon fibers differs between any of said two prepregs overlapping each other; and
said orientation of said carbon fibers of said prepreg of a lowermost layer of said top plate corresponding to a rear surface of said top plate is substantially same as said orientation of said carbon fibers of said prepregs of said anisotropic heat transfer plate.
5. The radiation imaging device according to claim 4, wherein said carbon fibers are pitch-based carbon fibers.
6. The radiation imaging device according to claim 4, wherein said top plate, said anisotropic heat transfer plate, and said detection panel are joined with pressure.
7. The radiation imaging device according to claim 4, wherein said top plate, said anisotropic heat transfer plate, and said detection panel are bonded to each other.
8. The radiation imaging device according to claim 7, wherein
said top plate and said anisotropic heat transfer plate are glued together with a first adhesive layer;
said anisotropic heat transfer plate and said detection panel are glued together with a second adhesive layer; and
at least one of said first and second adhesive layers is composed of plural adhesive sections arranged in a direction orthogonal to said orientation of said carbon fibers of said anisotropic heat transfer plate.
9. The radiation imaging device according to claim 8, wherein said anisotropic heat transfer plate is provided with a heat absorbing member on a side in said first direction.
10. The radiation imaging device according to claim 9, wherein said heat absorbing member is thermally bonded to said housing.
11. The radiation imaging device according to claim 4, wherein said housing is in shape of a box having a front frame and a rear frame, and said top plate is fitted into said front frame.
12. The radiation imaging device according to claim 11, wherein said front frame and said rear frame are made of metal.
13. The radiation imaging device according to claim 12, wherein
said anisotropic heat transfer plate and said radiation detector are attached to said front frame; and
a base board for blocking said radiation is attached to said rear frame, and at least one circuit board is mounted on a rear surface of said base board.
14. The radiation imaging device according to claim 13, wherein said detection panel and said circuit board are connected with at least one flexible cable, and said flexible cable extends from a side of said detection panel in said extending direction of said signal line, and said flexible cable is mounted with an IC chip designed for reading out said electric signal from each of said pixels of said detection panel.
15. The radiation imaging device according to claim 14, wherein said anisotropic heat transfer plate is provided with a heat absorbing member on a side in said first direction, and said heat absorbing member makes contact with said front frame of said housing.
16. The radiation imaging device according to claim 4, wherein each of said pixels has a photodiode made of amorphous silicon.
17. The radiation imaging device according to claim 4, wherein each of said pixels has a photodiode made of an organic photoelectric conversion material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor integrated circuit comprising:
a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal;
a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal;
a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and
a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.
2. The semiconductor integrated circuit according to claim 1, wherein the frequency determining unit is configured to select any one frequency region among a plurality of predetermined frequency regions by determining a frequency of the input clock, and configured to generate the frequency region signal.
3. The semiconductor integrated circuit according to claim 2, wherein the frequency determining unit includes:
a pulse generator configured to divide the frequency of the input clock and to generate a divided pulse signal using the frequency-divided clock;
a digital converter configured to sequentially delay the divided pulse signal and to generate a multiple-bit delay code by comparing phases of the delayed signals with the input clock;
an error detection corrector configured to generate a multiple-bit correction code by performing error detection and correction operations for the multiple-bit delay code;
an encoder configured to generate a multiple-bit encoding signal by encoding the multiple-bit correction code; and
a decoder configured to generate the frequency region signal by decoding the multiple-bit encoding signal.
4. The semiconductor integrated circuit according to claim 3, wherein the pulse generator is configured to divide the frequency of the input clock by two and to output only one period of the divided clock as the divided pulse signal.
5. The semiconductor integrated circuit according to claim 3, wherein the digital converter is configured to delay the divided pulse signal using a plurality of delayers connected in series, and configured to generate the multiple-bit delay code using a plurality of phase comparators that compare phases of the signals delayed by the delayers with the input clock, respectively.
6. The semiconductor integrated circuit according to claim 3, wherein the error detection corrector is implemented by a bubble error corrector and configured to generate the multiple-bit correction code by extracting a point where the logic values of the bits in the multiple-bit delay code are continuously at a predetermined value and then re-configuring a multiple-bit of code value.
7. The semiconductor integrated circuit according to claim 3, wherein the encoder is configured to generate the multiple-bit of encoding signal having a logic value that depends on that logic value of the multiple-bit of correction code that pertains to which range of predetermined frequency region.
8. The semiconductor integrated circuit according to claim 1, wherein the duty cycle control unit is configured to detect the duty cycle of the DLL clock, to generate a multiple-bit of digital signal corresponding to the detection result, to generate first and second bias currents in response to the multiple-bit of digital signal, and to output the first and second bias current as the duty cycle control signal.
9. The semiconductor integrated circuit according to claim 8, wherein the duty cycle control unit includes:
a duty cycle detector configured to detect the duty cycle of the DLL clock and generate a detection signal;
a counter configured to generate a multiple-bit counting signal by performing a counting operation in response to the detection signal; and
a current source configured to generate the first and second bias currents in response to the multiple-bit of counting signal, and to output the bias currents as the duty cycle control signal.
10. The semiconductor integrated circuit according to claim 9, wherein the current source includes:
a first node;
a second node;
a first current controller configured to control the amount of current of the first node in response to a supply current and the multiple-bit of counting signal;
a second current controller configured to control the amount of current of the second node in response to the supply current; and
a current generator configured to control the amount of current of the duty cycle control signal in accordance to the amount of current of the first node and to the amount of current of the second node.
11. The semiconductor integrated circuit according to claim 1, wherein the duty cycle correcting unit is configured to operate in a frequency region corresponding to the frequency region signals.
12. The semiconductor integrated circuit according to claim 11, wherein the duty cycle correcting unit includes:
a first node;
a second node;
a clock input section configured to control the voltage of the first node and the voltage of the second node in response to the input clock;
a first voltage controller configured to control the voltage of the first node in accordance to control of the frequency region signal and to the duty cycle control signal;
a second voltage controller configured to control the voltage of the second node in accordance to the frequency region signal and to the duty cycle control signal; and
a corrected clock generator configured to generate the corrected clock in response to the voltage levels of the first node and the second node.
13. A semiconductor integrated circuit comprising:
a frequency determining unit configured to generate a frequency region signal by determining a frequency of an input clock;
a duty cycle control unit, in response to the logic value of the multiple-bit digital signal, configured to generate a multiple-bit digital signal by detecting a duty cycle of a DLL clock, and configured to generate a first bias current having a variable current and configured to generate a second bias current having a substantially fixed current;
a duty cycle correcting unit configured to operate in a frequency region corresponding to the frequency region signal, configured to adjust the voltage levels of a first node and a second node in accordance to the amount of current of the first bias current and the amount of current of the second bias current, and configured to generate a corrected clock by correcting a duty cycle of the input clock in accordance to the voltage levels of the first node and the second node; and
a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.
14. The semiconductor integrated circuit according to claim 13, wherein the frequency determining unit includes:
a pulse generator configured to divide the frequency of the input clock and to generate a divided pulse signal using the frequency-divided clock;
a digital converter configured to sequentially delay the divided pulse signal and to generate a multiple-bit delay code by comparing phases of the delayed signals with the input clock;
an error detection corrector configured to generate a multiple-bit correction code by performing error detection and correction operation for the multiple-bit delay code;
an encoder configured to generate a multiple-bit encoding signal by encoding the multiple-bit correction code; and
a decoder configured to generate the frequency region signal by decoding the multiple-bit encoding signal.
15. The semiconductor integrated circuit according to claim 13, wherein the duty cycle control unit includes:
a duty cycle detector configured to detect the duty cycle of the DLL clock and to generate a detection signal;
a counter, in response to the detection signal, configured to generate a multiple-bit counting signal by performing a counting operation; and
a current source configured to generate first and second bias currents in response to the multiple-bit of counting signal.
16. The semiconductor integrated circuit according to claim 15, wherein the current source includes:
a third node;
a fourth node;
a first current controller, in response to a supply current and the multiple-bit of counting signal, configured to control the amount of current of the third node;
a second current controller, in response to the supply current, configured to control the amount of current of the fourth node; and
a current generator configured to control the amount of first and second bias currents in accordance to the amount of current of the third node and the amount of current of the fourth node.
17. The semiconductor integrated circuit according to claim 13, wherein the duty cycle correcting unit includes:
a clock input section, in response to the input clock, configured to control the voltage of the first node and to control the voltage of the second node;
a first voltage controller configured to control the voltage of the first node in accordance to the frequency region signal and to the first bias current;
a second voltage controller configured to control the voltage of the second node in according to the frequency region signal and the second bias current; and
a corrected clock generator configured to generate the corrected clock in response to the voltage levels of the first node and the second node.