1. A semiconductor memory device comprising:
a stacked memory cell array having a laminated plurality of memory cell layers, wherein each of the individual memory cell layers has a plurality of blocks;
a layer quality information storing circuit which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify the memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and
an address converting circuit in which if an externally input address input from outside corresponds to the block in the defective memory cell layer, the externally input address is address-converted so as to correspond to the block in the normal memory cell layer.
2. The semiconductor memory device according to claim 1, further comprising switching circuits, each of which is provided for each of the blocks, and allows or prevents a connection between the block and a row control circuit which applies a predetermined voltage to a word line of the block.
3. The semiconductor memory device according to claim 2, further comprising:
a block address generating circuit which generates a block address of the block in the defective memory cell layer based on the layer quality information stored in the layer quality information storing circuit;
wherein the switching circuit prevents the connection between the block corresponding to the block address and the row control circuit.
4. The semiconductor memory device according to claim 2, further comprising:
a multiplexer circuit which generates one layer selection signal distributed to each of the switching circuits corresponding to each of the blocks in the memory cell layer based on the layer quality information stored in the layer quality information storing circuit, the layer selection signal being generated for each of the memory cell layers, wherein the layer selection signal is a first signal when the memory cell layer containing the block is the normal memory cell layer, and the layer selection signal is a second signal when the memory cell layer containing the block is the defective memory cell layer,
wherein the switching circuit prevents the connection between the row control circuit and the block when the layer selection signal is the second signal.
5. The semiconductor memory device according to claim 2, further comprising:
level shifter circuits, each of which is provided for each of the memory cell layers, wherein a gate voltage common to a plurality of the memory cell layers is input, the gate voltage being required for the switching circuit to allow the connection between the row control circuit and the block, wherein based on the layer quality information stored in the layer quality information storing circuit, each of the level shifter circuits outputs the gate voltage to the switching circuit corresponding to the block in the normal memory cell layer and does not output the gate voltage to the switching circuit corresponding to the block in the defective memory cell layer.
6. A semiconductor memory device comprising:
a memory chip which has:
a stacked memory cell array having a laminated plurality of memory cell layers, wherein each of the individual memory cell layers has a plurality of blocks; and
a layer quality information storing circuit which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify the memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and
a controller which adds a control signal and an address to the memory chip and sends and receives data to and from the memory chip, wherein based on the layer quality information stored in the layer quality information storing circuit, the controller determines whether the address to be added to the memory chip corresponds to the normal memory cell layer or corresponds to the defective memory cell layer, and does not provide an access to the address which is determined to correspond to the defective memory cell layer.
7. The semiconductor memory device according to claim 6, further comprising switching circuits, each of which is provided for each of the blocks, and allows or prevents a connection between the block and a row control circuit which applies a predetermined voltage to a word line of the block.
8. The semiconductor memory device according to claim 7, further comprising:
a block address generating circuit which generates a block address of the block in the defective memory cell layer based on the layer quality information stored in the layer quality information storing circuit;
wherein the switching circuit prevents the connection between the block corresponding to the block address and the row control circuit.
9. The semiconductor memory device according to claim 7, further comprising:
a multiplexer circuit which generates one layer selection signal distributed to each of the switching circuits corresponding to each of the blocks in the memory cell layer based on the layer quality information stored in the layer quality information storing circuit, the layer selection signal being generated for each of the memory cell layers, wherein the layer selection signal is a first signal when the memory cell layer containing the block is the normal memory cell layer, and the layer selection signal is a second signal when the memory cell layer containing the block is the defective memory cell layer,
wherein the switching circuit prevents the connection between the row control circuit and the block when the layer selection signal is the second signal.
10. The semiconductor memory device according to claim 7, further comprising:
level shifter circuits, each of which is provided for each of the memory cell layers, wherein a gate voltage common to a plurality of the memory cell layers is input, the gate voltage being required for the switching circuit to allow the connection between the row control circuit and the block, wherein based on the layer quality information stored in the layer quality information storing circuit, each of the level shifter circuits outputs the gate voltage to the switching circuit corresponding to the block in the normal memory cell layer and does not output the gate voltage to the switching circuit corresponding to the block in the defective memory cell layer.
11. A semiconductor memory device comprising:
a memory chip which has:
a stacked memory cell array having a laminated plurality of memory cell layers, wherein each of the individual memory cell layers has a plurality of blocks;
a layer quality information storing circuit which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify the memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and
switching circuits, each of which is provided for each of the blocks, prevents the connection between the block in the defective memory cell layer and the row control circuit and allows the connection between the block in the normal memory cell layer and the row control circuit; and
a controller which adds a control signal and an address to the memory chip, and sends and receives data to and from the memory chip, wherein after the switching circuits in the memory chip prevent the connection between the block in the defective memory cell layer and the row control circuit, the controller reads all the memory cell layers and, based on the read result, recognizes the defective memory cell layer, and does not provide the subsequent access to the recognized defective memory cell layer.
12. The semiconductor memory device according to claim 11, wherein the memory chip further includes a block address generating circuit which generates a block address of the block in the defective memory cell layer based on the layer quality information stored in the layer quality information storing circuit;
wherein the switching circuit prevents the connection between the block corresponding to the block address and the row control circuit.
13. The semiconductor memory device according to claim 11, wherein the memory chip further includes a multiplexer circuit which generates one layer selection signal distributed to each of the switching circuits corresponding to each of the blocks in the memory cell layer based on the layer quality information stored in the layer quality information storing circuit, the layer selection signal being generated for each of the memory cell layers, wherein the layer selection signal is a first signal when the memory cell layer containing the block is the normal memory cell layer, and the layer selection signal is a second signal when the memory cell layer containing the block is the defective memory cell layer,
wherein the switching circuit prevents the connection between the row control circuit and the block when the layer selection signal is the second signal.
14. The semiconductor memory device according to claim 11, wherein the memory chip further includes level shifter circuits, each of which is provided for each of the memory cell layers, wherein a gate voltage common to a plurality of the memory cell layers is input, the gate voltage being required for the switching circuit to allow the connection between the row control circuit and the block, wherein based on the layer quality information stored in the layer quality information storing circuit, each of the level shifter circuits outputs the gate voltage to the switching circuit corresponding to the block in the normal memory cell layer and does not output the gate voltage to the switching circuit corresponding to the block in the defective memory cell layer.
15. A semiconductor memory device comprising:
a memory chip which has:
a stacked memory cell array having a laminated plurality of memory cell layers, wherein each of the individual memory cell layers has a plurality of blocks;
a layer quality information storing circuit which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify the memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers;
a sense amplifier circuit having a latch circuit for holding data output from a bit line before the data is output to a data inputoutput line; and
a state machine which refers to the layer quality information storing circuit, and if the data is read from the block in the normal memory cell layer, outputs the first data or the second data held in the latch circuit to the data inputoutput line, while if the data is read from the block in the defective memory cell layer, outputs the first data to the data inputoutput line by controlling the latch circuit; and
a controller which adds a control signal and an address to the memory chip and sends and receive data to and from the memory chip, wherein the controller reads all the memory cell layers, and if all the data read from the block through the data inputoutput line is the first data, the controller recognizes the block as a defective block and does not provide the subsequent access to the recognized defective block.
16. The semiconductor memory device according to claim 1, wherein memory cells in the individual memory cell layer are non-volatile MOS transistors.
17. The semiconductor memory device according to claim 1, wherein each of the memory cells in the individual memory cell layers is configured by connecting a non-ohmic element and a variable resistance element in series.
18. The semiconductor memory device according to claim 17, wherein the stacked memory cell array is configured by laminating a plurality of the memory cell layers in a cross point structure.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A thermally-assisted magnetic recording head comprising:
a medium facing surface that faces a magnetic recording medium;
a main pole that has a front end face located in the medium facing surface and produces a write magnetic field for writing data on the magnetic recording medium;
a waveguide including a core and a cladding, the core allowing light to propagate therethrough; and
a plasmon generator having a near-field light generating part located in the medium facing surface, the plasmon generator being configured so that a surface plasmon is excited on the plasmon generator based on the light propagating through the core and the near-field light generating part generates near-field light based on the surface plasmon, wherein:
the plasmon generator and the core are disposed to align in a direction of travel of the magnetic recording medium;
the core has an end face that faces toward the medium facing surface and that is located away from the medium facing surface;
the main pole is interposed between the end face of the core and the medium facing surface;
the front end face includes a first end and a second end that are opposite to each other in a track width direction which is a direction parallel to the medium facing surface and perpendicular to the direction of travel of the magnetic recording medium;
in a region sandwiched between a first virtual plane passing through the first end and perpendicular to the medium facing surface and to the track width direction and a second virtual plane passing through the second end and perpendicular to the medium facing surface and to the track width direction, an arbitrary cross section of the main pole that passes through an arbitrary point on the front end face and is perpendicular to the medium facing surface and to the track width direction has a length in a direction perpendicular to the medium facing surface; and
a third length is smaller than a first length and a second length and is a minimum of the length of the arbitrary cross section obtained with the arbitrary point varied, where the first length is the length of the arbitrary cross section when the arbitrary point is located at the first end, the second length is the length of the arbitrary cross section when the arbitrary point is located at the second end, and the third length is the length of the arbitrary cross section when the arbitrary point is located at a center of the front end face in the track width direction.
2. The thermally-assisted magnetic recording head according to claim 1, wherein the main pole includes two portions located on opposite sides of the center of the front end face in the track width direction, and in the two portions, the length of the arbitrary cross section increases with increasing distance between the arbitrary point and the center of the front end face in the track width direction.
3. The thermally-assisted magnetic recording head according to claim 2, wherein the two portions are in contact with each other at the center of the front end face in the track width direction, and the length of the arbitrary cross section increases as the arbitrary point shifts toward the first end from the center of the front end face in the track width direction, and increases as the arbitrary point shifts toward the second end from the center of the front end face in the track width direction.
4. The thermally-assisted magnetic recording head according to claim 1, wherein the main pole and the plasmon generator are disposed such that a virtual straight line passing through the center of the front end face in the track width direction and parallel to the direction of travel of the magnetic recording medium passes through the near-field light generating part.
5. The thermally-assisted magnetic recording head according to claim 1, wherein:
in the region sandwiched between the first virtual plane and the second virtual plane, a distance between the medium facing surface and an arbitrary point on the end face of the core varies as the arbitrary point on the end face of the core shifts along the track width direction; and
the main pole further has a rear end face opposite to the front end face, the rear end face having a shape defined by the end face of the core.
6. The thermally-assisted magnetic recording head according to claim 1, wherein the front end face has a length of 60 nm or more in the track width direction.
7. The thermally-assisted magnetic recording head according to claim 1, wherein the first length and the second length are equal, and the third length is 30% or more and less than 100% of the first and second lengths.
8. The thermally-assisted magnetic recording head according to claim 1, wherein the first length and the second length are equal, and the third length is 30% or more and no more than 75% of the first and second lengths.
9. The thermally-assisted magnetic recording head according to claim 1, wherein the first length and the second length are equal, and the third length is 37.5% or more and no more than 50% of the first and second lengths.
10. A head gimbal assembly comprising the thermally-assisted magnetic recording head according to claim 1, and a suspension that supports the thermally-assisted magnetic recording head.
11. A magnetic recording device comprising: a magnetic recording medium; the thermally-assisted magnetic recording head according to claim 1; and a positioning device that supports the thermally-assisted magnetic recording head and positions the thermally-assisted magnetic recording head with respect to the magnetic recording medium.