1. A capacitor structure comprising:
a first conductive layer having a first area;
at least one dielectric layer having a second area less than said first area provided on said first conductive layer, said at least one dielectric layer concentric with said first conductive layer and said first conductive layer having an exposed surface surrounding said at least one dielectric layer; and
a second conductive layer provided on said at least one dielectric layer, said second conductive layer having a third area less than said second area of said at least one dielectric layer and said second conductive layer concentric with said at least one dielectric layer.
2. The capacitor structure of claim 1 wherein said first conductive layer comprises polysilicon.
3. The capacitor structure of claim 2 wherein said second conductive layer comprises metal.
4. The capacitor structure of claim 2 wherein said second conductive layer comprises polysilicon.
5. The capacitor structure of claim 1 wherein said at least one dielectric layer comprises an exposed surface having a width of at least about 0.1 \u03bcm.
6. The capacitor structure of claim 1 wherein said at least one dielectric layer comprises a first dielectric layer provided on said first conductive layer and a second dielectric layer provided on said first dielectric layer.
7. The capacitor structure of claim 6 wherein said first dielectric layer comprises SiO2 and has a thickness of about 250 angstroms and said second dielectric layer comprises Si3N4 and has a thickness of about 320 angstroms.
8. A method of fabricating a capacitor structure, comprising:
providing a first conductive layer;
providing at least one dielectric layer on said first conductive layer;
providing a second conductive layer on said at least one dielectric layer;
etching said second conductive layer and said at least one dielectric layer to a first width; and
etching said second conductive layer to a second width less than said first width.
9. The method of claim 8 wherein said first conductive layer comprises polysilicon.
10. The method of claim 8 wherein said second conductive layer comprises metal.
11. The method of claim 8 wherein said second conductive layer comprises polysilicon.
12. The method of claim 8 wherein said second width is at least about 0.1 \u03bcm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A solid-state imaging device comprising:
a floating diffusion provided in a surface of a semiconductor layer;
a transfer gate extending inward from the surface of the semiconductor layer and bending in the semiconductor layer toward the floating diffusion side; and
a photoelectric conversion element provided in part of the semiconductor layer on the opposite side of the transfer gate from the floating diffusion and stretching from the side-surface side of the transfer gate to a position under the bottom thereof.
2. The solid-state imaging device according to claim 1, wherein the transfer gate comprises:
a first gate portion extending inward from the surface of the semiconductor layer; and
a comb-tooth-shaped second gate portion extending from the bottom of the first gate portion in a different direction from the extending direction of the first gate portion.
3. The solid-state imaging device according to claim 2, wherein the second gate portion extends along a planar direction of the semiconductor layer, so that the tip thereof reaches further into the floating diffusion side than the end on the first gate portion side of the floating diffusion in see-through plan view.
4. The solid-state imaging device according to claim 2, wherein a plurality of the first gate portions and a plurality of the second gate portions are formed in comb-tooth shapes.
5. The solid-state imaging device according to claim 4, wherein a plurality of the floating diffusions are provided in such a way that the floating diffusions and the comb-tooth shaped second gate portions are alternately arranged in see-through plan view.
6. The solid-state imaging device according to claim 5, comprising a connection connecting the plurality of the floating diffusions.
7. The solid-state imaging device according to claim 6, wherein the plurality of the floating diffusions are connected by the connection extending over a row of the floating diffusions arranged in a line.
8. The solid-state imaging device according to claim 6, wherein the plurality of the floating diffusions are connected by the connection embedded on the opposite side of the floating diffusions from the first gate portions.
9. The solid-state imaging device according to claim 5, comprising:
contact plugs provided on the plurality of the floating diffusions;
an interlayer insulating film provided on the semiconductor layer; and
a line provided in the interlayer insulating film to connect the contact plugs.
10. The solid-state imaging device according to claim 2, comprising an electrode pad touching an end face of the first gate portion, the end face being on the front surface side of the semiconductor layer.
11. The solid-state imaging device according to claim 2, wherein the photoelectric conversion element comprises:
a semiconductor area of a first conductivity type that extends from the surface of the semiconductor layer more deeply than the bottom surface of the second gate portion; and
a semiconductor area of a second conductivity type whose top is in contact with the bottom surface of the semiconductor area of the first conductivity type.
12. The solid-state imaging device according to claim 11, wherein the first conductivity type is a P type, and the second conductivity type is an N type, and
wherein the photoelectric conversion element has a planar PN junction located deeper in the semiconductor layer than the bottom surface of the transfer gate.
13. The solid-state imaging device according to claim 2, wherein the photoelectric conversion element comprises:
a first charge storage area located on one side-surface side of the first gate portion; and
a second charge storage area located under the bottom surface of the second gate portion.
14. The solid-state imaging device according to claim 13, wherein the second charge storage area extends along the bottom surface of the second gate portion to such a position that it has an overlap with the floating diffusion one above the other.
15. The solid-state imaging device according to claim 2, wherein the first gate portion extends in a thickness direction of the semiconductor layer, and the second gate portion extends in a direction perpendicular to the extension direction of the first gate portion.
16. The solid-state imaging device according to claim 1, wherein the transfer gate is coated on the outer surfaces with insulating material.