1. A method for graphically assisting navigation of a medical instrument in a magnetic resonance device within a medical procedure region in a patient in the magnetic resonance device comprising the steps of:
operating the magnetic resonance device with the patient therein to obtain a high-contrast image data set representing said procedure region;
supplying said high-contrast image data set to a computerized processor and, in said computerized processor, automatically determining, from said high-contrast image data set, coordinates of a target, selected from the group consisting of a target position and a target region, to be reached by the instrument in said procedure region;
operating said magnetic resonance device to repeatedly acquire low-contrast image data representing said instrument during movement of said instrument in said procedure region towards said target;
calibrating a position determination device to bring position determination algorithms implemented in the position determination device into registration with a coordinate system associated with the magnetic resonance device;
supplying said low-contrast image data to said computerized position determination device and, in said position determination device, implementing said position determination algorithm to identify a position and orientation of said instrument relative to the coordinate system of the magnetic resonance device during said movement; and
at a display device in communication with said computerized processor and said computerized position determination device, representing at least a relative position and orientation of said instrument relative to said target, using said coordinates of said target and at least one of said low-contrast image data and said position and orientation of said instrument.
2. A method as claimed in claim 1 comprising representing said target at said display with a symbolic marking indicating an orientation of said target.
3. A method as claimed in claim 2 comprising presenting a representation at said display comprising a slice image of said low-contrast data, and entering said symbolic marking into said slice image when reconstruction said slice image.
4. A method as claimed in claim 2 comprising employing a marking representing information identifying a distance of the target position perpendicular to the slice plane.
5. A method as claimed in claim 4 wherein said marking has a shape, a color, and a size, and comprising configuring at least one of said shape and said color of said marking to indicate a position of the target above or below the plane of the slice image, and indicating the distance of the target from the plane of the slice by said size of said marking.
6. A method as claimed in claim 1 comprising forming said low-contrast image data from two slice images.
7. A method as claimed in claim 6 comprising forming said low-contrast data from two slice images that are substantially perpendicular to each other.
8. A method as claimed in claim 1 comprising incorporating at least one additional subject or area in said representation, having known coordinates in said high-contrast image data set.
9. A method as claimed in claim 1 comprising, in said processor, automatically determining at least one of a future position and a movement line of said instrument from said position and orientation of said instrument, and incorporating a representation of at least one of said future position and said movement line in said representation at said display.
10. A method as claimed in claim 1, comprising, in said processor, determining geometric parameters in said computerized processor that characterize said instrument relative to said target, and incorporating said geometric parameters in said representation at said display.
11. A magnetic resonance device for graphically assisting navigation of a medical instrument within a medical procedure region in a patient in the magnetic resonance device comprising:
a magnetic resonance data acquisition device configured to receive the patient therein;
a control unit that operates the magnetic resonance device with the patient therein to obtain a high-contrast image data set representing said procedure region;
a computerized processor supplied with said high-contrast image data set, configured to automatically determine, from said high-contrast image data set, coordinates of a target, selected from the group consisting of a target position and a target region, to be reached by the instrument in said procedure region;
said control unit being configured to operate said magnetic resonance device to repeatedly acquire low-contrast image data representing said instrument during movement of said instrument in said procedure region towards said target;
a position determination device calibrated to bring position determination algorithms implemented in the position determination device into registration with a coordinate system associated with the magnetic resonance device;
said low-contrast image data being supplied to said computerized position determination device, said position determination device being configured to implement said position determination algorithms to identify a position and orientation of said instrument relative to the coordinate system of the magnetic resonance device during said movement; and
a display device in communication with said computerized processor and said computerized position determination device, at which at least a relative position and orientation of said instrument relative to said target is displayed, using said coordinates of said target and at least one of said low-contrast image data and said position and orientation of said instrument.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic chip comprising at least:
an electronic circuit located at a front face of a substrate;
at least one capacitive element placed at least at a back face of the substrate and at least partly facing the electronic circuit, and electrically connected to the electronic circuit by at least one first electrical connection and one second electrical connection, the first electrical connection including at least one first electrically conducting via passing through the substrate, the electronic circuit being capable of measuring the value of the electrical capacitance of the capacitive element between the first and the second electrical connections, and
at least one second via or a trench passing through the back face of the substrate and a part of the thickness of the substrate, and facing the electronic circuit such that a bottom wall of the second via or of the trench are separated from the electronic circuit by a non-zero distance.
2. The electronic chip according to claim 1, in which the second electrical connection comprises at least one third electrically conducting via passing through the substrate or comprises at least part of the substrate that is electrically conducting or semiconducting.
3. The electronic chip according to claim 1, in which the distance between the bottom wall of the second via or the trench and the electronic circuit is less than or equal to about 20 \u03bcm.
4. The electronic chip according to claim 1, comprising at least:
a first dielectric layer covering the side walls of the first electrically conducting via, the side walls and the bottom wall of the second via or the trench, and the back face of the substrate,
a first continuous electrically conducting layer covering the first dielectric layer on the side walls of the first electrically conducting via, the side walls and the bottom wall of the second via or trench, and at least part of the back face of the substrate, and also covering a bottom wall of the first electrically conducting via,
in which the first electrically conducting layer forms a first electrode of the capacitive element and is electrically connected to the electronic circuit through the first electrical connection.
5. The electronic chip according to claim 4, in which part of the substrate placed in contact with the first dielectric layer and facing the first electrically conducting layer forms a second electrode of the capacitive element.
6. The electronic chip according to claim 4, in which the first dielectric layer and the first electrically conducting layer completely fill the volumes formed by at least one of the first electrically conducting via, the second via or trench.
7. The electronic chip according to claim 4, also comprising a second structured electrically conducting layer at the front face of the substrate, forming a coil inductively coupled to at least part of the first electrically conducting layer, the second electrically conducting layer being electrically connected to the electronic circuit that can measure the value of an inductance of the coil.
8. The electronic chip according to claim 7, in which said part of the first electrically conducting layer corresponds to the part located at the bottom wall of the second via or the trench.
9. The electronic chip according to claim 4, in which the first electrically conducting layer comprises a material which is not transparent to wavelengths between about 100 nm and 10 \u03bcm.
10. The electronic chip according to claim 1, in which the capacitive element comprises at least:
a first plane electrically conducting portion located at the back face of the substrate, forming a first electrode of the capacitive element and electrically connected to the electronic circuit;
a second dielectric layer covering at least the first plane electrically conducting portion;
a second plane electrically conducting portion separated from the first plane electrically conducting portion by the second dielectric layer, forming a second electrode of the capacitive element and electrically connected to the first electrically conducting via.
11. The electronic chip according to claim 2, comprising at least one third plane electrically conducting portion separated from the first plane electrically conducting portion by the second dielectric layer and electrically connected to the electronic circuit through at least the third electrically conducting via passing through the substrate, and in which the first plane electrically conducting portion and the third plane electrically conducting portion form a first electrode and a second electrode respectively of a second capacitive element located at the back face of the substrate and at least partly facing the electronic circuit.
12. The electronic chip according to claim 2, in which the first plane electrically conducting portion is in contact with an electrically conducting material that fills at least the second via or the trench and is electrically connected to the electronic circuit through at least the third electrically conducting via passing through the substrate.
13. The electronic chip according to claim 10, in which the first plane electrically conducting portion is connected to the electronic circuit through at least a part of the substrate which is electrically conducting or semiconducting.
14. The electronic chip according to claim 1, comprising several second vias or trenches passing through the back face of the substrate and part of the thickness of the substrate and having different dimensions.
15. A method of manufacturing an electronic chip comprising at least the following steps:
formation of an electronic circuit at a front face of a substrate;
fabrication of at least one capacitive element at at least one back face of the substrate and at least partly facing the electronic circuit, and at least one first electrical connection and one second electrical connection such that the first electrical connection comprises at least one first electrically conducting via passing through the substrate and electrically connecting the capacitive element to the electronic circuit, the electronic circuit being capable of measuring the value of the electrical capacitance of the capacitive element between the first electrical connection and the second electrical connection, and
fabrication of at least one second via or trench passing through the back face of the substrate and part of the thickness of the substrate, and located facing the electronic circuit such that a bottom wall of the second via or the trench is at a non-zero distance from the electronic circuit.
16. The method according to claim 15, including the fabrication of several second vias or trenches passing through the back face of the substrate and part of the thickness of the substrate, the dimensions of each of the second vias or trenches being chosen randomly relative to the dimensions of the other second vias or trenches.
17. The method according to claim 15, comprising fabrication of at least one third electrically conducting via passing through the substrate and that will form at least part of the second electrical connection.