1. A processorcache assembly, comprising:
a first semiconductor die having an array of processing units, wherein:
each processing unit of the array of processing units has a set of processor contact pads;
the set of processor contact pads are conductive pads on a surface of the first semiconductor die;
each set of processor contact pads is unique from the set of processor contact pads of all other processing units of the array of processing units; and
each set of the processor contact pads includes a first subset of processor contact pads for address signals and a second subset of processor contact pads for data signals; and
a second semiconductor die having an array of cache units, wherein:
each cache unit of the array of cache units has a set of cache contact pads;
the set of cache contact pads are conductive pads on a surface external of the second semiconductor die;
each set of cache contact pads is unique from the set of cache contact pads of all other cache units of the array of cache units;
each set of the external contact pads includes a first subset of cache contact pads for address signals and a second subset of cache contact pads for data signals;
the first subset of cache contact pads of each cache unit is connected to the first subset of processor contact pads of a unique one of the processor units; and
the second subset of cache contact pads of each cache unit is connected to the second subset of processor contact pads of the processor unit to which its first subset of cache contact pads is connected.
2. The processorcache assembly of claim 1, wherein:
the first semiconductor die has a major surface;
the processor contact pads are on the major surface of the first semiconductor die;
the second semiconductor die has a major surface;
the cache contact pads are on the major surface of the second semiconductor die; and
the major surface of the first semiconductor die faces the major surface of the second semiconductor die.
3. The processorcache assembly of claim 2, wherein the processor contact pads are directly connected to the cache contact pads through conductive bumps.
4. The processorcache assembly of claim 3, wherein the first semiconductor die is further characterized as having a greater surface area than the second semiconductor die.
5. The processorcache assembly of claim 4, wherein the first semiconductor die has external contact pads along a periphery of the first semiconductor die for making external connections from the first semiconductor die.
6. The processorcache assembly of claim 2, further comprising an interposer between each major surface of the first semiconductor die and the second semiconductor die for connecting the processor contact pads to the cache contact pads.
7. The processorcache assembly of claim 6, wherein the interposer has traces for carrying power to at least one of a group consisting of the first semiconductor die and the second semiconductor die.
8. The processorcache assembly of claim 7, wherein the interposer extends beyond an outer boundary of the first semiconductor die and the second semiconductor die.
9. The processorcache assembly of claim 1, wherein the processing units have a first area and the cache units have a second area, wherein the first area and the second area are substantially the same.
10. The processorcache assembly of claim 9, wherein outer boundaries of the processing units and the cache units are coterminous.
11. The processorcache assembly of claim 1, wherein each of the processing units is the same shape and size as all other processing units.
12. The processorcache assembly of claim 1, wherein the array of processing units has a first geometric shape and the array of cache units has a second geometric shape that is a mirror image of the first geometric shape.
13. A method of making a processorcache assembly, comprising:
forming a processor die having an array of processor units being in a first arrangement and having a first plurality of contact pads in a second arrangement;
forming a cache die having an array of cache units being in a third arrangement and having a second plurality of contact pads in a fourth arrangement; wherein
the third arrangement is a mirror image of the first arrangement; and
the fourth arrangement is a mirror image of the second arrangement; and contacting the processor die to the cache die.
14. The method of claim 13, wherein:
the step of forming the processor die is further characterized by the first plurality of contact pads comprising a plurality of processor sets of contact pads wherein each processor set is unique to one of the processor units and comprises a first subset of contact pads for carrying an address; and
the step of forming the cache die is further characterized by a second plurality of contact pads comprising a plurality of cache sets of contact pads wherein each cache set is unique to one of the cache units and comprises a second subset of contact pads for carrying an address.
15. The method of claim 14, wherein the step of contacting the processor die to the cache die causes each of the processor units to be coterminous with a unique one of the cache units.
16. The method of claim 14, wherein the step of contacting the processor die to the cache die directly connects the first plurality of contact pads to the second plurality of contact pads through a plurality of solder bumps.
17. The method of claim 14, wherein the step of contacting is further characterized by providing an interposer and connecting the processor die and the cache die to the interposer.
18. A processorcache assembly, comprising:
a processor die having first, second, third, and fourth processor units arranged in an array of processor units;
first, second, third, and fourth sets of processor contact pads on a first major surface of the processor die, wherein the first, second, third, and fourth sets of processor contact pads are for carrying addresses from the first, second, third, and fourth processor units, respectively;
a cache die having first, second, third, and fourth cache units arranged in an array of cache units;
first, second, third, and fourth sets of cache contact pads on a first major surface of the cache die, wherein the first, second, third, and fourth sets of cache contact pads are for receiving addresses from the first, second, third, and fourth processor units, respectively, for the use of the first, second, third, and fourth cache units, respectively.
19. The processorcache assembly of claim 18, further comprising:
fifth, sixth, seventh, and eighth sets of processor contact pads on the first major surface of the processor die, wherein the fifth, sixth, seventh, and eighth sets of processor contact pads are for carrying data to and from the first, second, third, and fourth processor units, respectively; and
fifth, sixth, seventh, and eighth sets of cache contact pads on the first major surface of the cache die, wherein the fifth, sixth, seventh, and eighth sets of cache contact pads are for carrying data to and from the first, second, third, and fourth cache units, respectively.
20. The processorcache assembly of claim 18, wherein the first, second, third, and fourth cache units are caches dedicated to use by the first, second, third, and fourth processor units, respectively.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An input and output (IO) circuit comprising:
an output buffer having an NMOS transistor coupled to a PMOS transistor;
an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein, and coupled to the output buffer; and
a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground,
wherein a voltage drop across the diode string increases the SCR holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.
2. The circuit of claim 1 wherein the number of the diodes in the diode string is determined by a positive supply voltage and the SCR holding voltage.
3. The circuit of claim 1 wherein the NMOS transistor is realized by using two asymmetric NMOS transistors.
4. The circuit of claim 1 wherein the NMOS transistor is realized by using a transistor layout for enhancing a turn-on speed of the ESD protection circuit.
5. The circuit of claim 1 wherein the SCR has an increased beta-gain product of two transistors therein.
6. The circuit of claim 1 wherein the diode string has two or fewer diodes for a positive supply voltage of about 2.5V or less.
7. The circuit of claim 1 wherein the diode string has four, or fewer diodes, for a positive supply voltage of about 3.3V or less.
8. An input and output (IO) circuit comprising:
an output buffer having an NMOS transistor coupled to a PMOS transistor;
an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer; and
a diode string having four, or fewer diodes, coupled between a source node of the NMOS transistor and ground,
wherein a voltage drop across the diode string increases the SCR holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.
9. The circuit of claim 8 wherein the number of the diodes in the diode string is determined by a positive supply voltage and the SCR gate holding voltage.
10. The circuit of claim 8 wherein the NMOS transistor is realized by using two asymmetric NMOS transistors.
11. The circuit of claim 8 wherein the NMOS transistor is realized by using a transistor layout for enhancing a turn-on speed of the ESD protection circuit.
12. The circuit of claim 8 wherein the SCR has an increased beta-gain product of two transistors therein.
13. A layout for an output buffer having an NMOS transistor comprising:
a N well region having a P+ region contained therein; and
two asymmetrical NMOS transistors formed on two sides of the P+ region;
wherein a portion of the P+ region in the N well region provides at least one resistor for a parasitic silicon controlled rectifier (SCR), and
wherein a diode string having a predetermined number of diodes is coupled between a source node of the NMOS transistors and ground.
14. The layout of claim 13 wherein the number of the diodes in the diode string is determined by a positive supply voltage and the SCR gate holding voltage.
15. The layout of claim 13 wherein the SCR has an increased beta-gain product of two transistors therein.
16. The layout of claim 13 wherein the diode string has two or fewer diodes for a positive supply voltage of about 2.5V or less.
17. The layout of claim 13 wherein the diode string has four, or fewer diodes, for a positive supply voltage of about 3.3V or less.
18. The layout of claim 13 further comprising one or more guard rings for collecting minority carriers.
19. The layout of claim 13 wherein a center portion of the P+region is connected to an inputoutput pad.