1. A passive component incorporating interposer comprising:
a resin substrate having wiring layers on both surfaces;
one or more passive components mounted on the wiring layer on one surface of the resin substrate;
a first insulating layer made of woven fabric or non-woven fabric and thermosetting resin laminated on the other surface of the resin substrate not mounted with the passive component;
a second insulating layer made of woven fabric or non-woven fabric and thermosetting resin laminated on the surface of the resin substrate mounted with the passive component and formed with a space larger than an outside dimension of the passive component;
a first wiring layer formed on a surface of the first insulating layer not contacting the resin substrate;
a second wiring layer formed on a surface of the second insulating layer not contacting the resin substrate; and
a through hole for electrically connecting the wiring layers disposed on both sides of the resin substrate, the first wiring layer, and the second wiring layer; wherein
the first wiring layer is formed to enable mounting of a semiconductor element.
2. A passive component incorporating interposer comprising:
a resin substrate having wiring layers on both surfaces;
one or more passive components mounted on the wiring layer on one surface of the resin substrate;
a first insulating layer made of inorganic filler and thermosetting resin laminated on the other surface of the resin substrate not mounted with the passive component;
a second insulating layer made of inorganic filler and thermosetting resin laminated on the surface of the resin substrate mounted with the passive component;
a first wiring layer formed on a surface of the first insulating layer not contacting the resin substrate;
a second wiring layer formed on a surface of the second insulating layer not contacting the resin substrate; and
a through hole for electrically connecting wiring layers disposed on both surfaces of the resin substrate, the first wiring layer, and the second wiring layer; wherein
the first wiring layer is formed to enable mounting of a semiconductor element.
3. The passive component incorporating interposer according to claim 1, wherein the passive component is at least a chip capacitor.
4. The passive component incorporating interposer according to claim 1, wherein the passive component is a chip capacitor and a chip resistor.
5. The passive component incorporating interposer according to claim 2, wherein the passive component is at least a chip capacitor.
6. The passive component incorporating interposer according to claim 2, wherein the passive component is a chip capacitor and a chip resistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
determining an initial phase offset between a center track and a side track;
using a processor to determine an initial side track pulse shape, using the initial phase offset and side track interference, wherein the initial side track pulse shape minimizes a contribution of the side track interference to a center track bit; and
removing the contribution of the side track interference from the center track bit using the initial side track pulse shape and the side track interference.
2. The method of claim 1, wherein the center track and the side track are associated with a shingled magnetic recording (SMR) system.
3. The method of claim 1, wherein determining the initial phase offset includes using
L
^
N
–
1
=
m
^
N
–
1
+
L
2
+
1
,
where {circumflex over (m)}N\u22121=arg maxmsmN\u22121 and smN\u22121=\u03a3i=0L|Ci+mN\u22121|.
4. The method of claim 1, wherein using the processor to determine the initial side track pulse shape includes using a correlation metric CmN\u22121=\u03a3k=1TykNbk\u2212mN\u22121, where T is a number of samples used for the correlation.
5. The method of claim 1, wherein determining the initial phase offset includes using
L
^
N
–
1
=
L
max
2
+
1
–
i
max
,
where imax=arg maxi\u0125iLMSN\u22121 and Lmax is the length of the initial side track pulse shape.
6. The method of claim 1, wherein using the processor to determine the initial side track pulse shape includes using \u0125LMSN\u22121=arg min hN\u22121E|ek1|2, where ek1=ykN\u2212\u03a3i=\u2212LmaxLmaxhiN\u22121bk\u2212iN\u22121 and Lmax is the length of the initial side track pulse shape.
7. The method of claim 1, wherein using the processor to determine the initial side track pulse shape includes using \u0125k+1LMSN\u22121= \u0125kLMSN\u22121+\u03bc1\xd7ek1\xd7 bkN\u22121, where ek1=ykN\u2212\u03a3i=\u2212LmaxLmaxhiN\u22121bk\u2212iN\u22121, Lmax is the length of the initial side track pulse shape, \u03bc1 is an adaptation coefficient, and bkN\u22121=bk\u2212LmaxN\u22121 . . . bk+LmaxN\u22121.
8. The method of claim 1, further comprising:
using the processor to determine a second side track pulse shape, using the initial side track pulse shape and the side track data, wherein the second side track pulse shape minimizes the contribution of the side track interference to a second center track bit; and
remove the contribution of the side track interference from the second center track bit using the second side track pulse shape and side track data.
9. The method of claim 8, wherein using the processor to determine the second side track pulse shape includes using \u0125k+1LMSN\u22121= \u0125kLMSN\u22121+\u03bc5\xd7ek5\xd7 bkN\u22121, where ek5=ykN\u2212\u03a3i=\u2212LLhiN\u22121bk\u2212i\u2212{circumflex over (L)}N\u22121N\u22121 is an adaptation coefficient.
10. A system, comprising:
a processor; and
a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:
determine an initial phase offset between a center track and a side track;
determine an initial side track pulse shape, using the initial phase offset and side track interference, wherein the initial side track pulse shape minimizes a contribution of the side track interference to a center track bit; and
remove the contribution of the side track interference from the center track bit using the initial side track pulse shape and the side track interference.
11. The system of claim 10, wherein the system is associated with shingled magnetic recording (SMR).
12. The system of claim 10, wherein the instructions for determining the initial phase offset include instructions for using
L
^
N
–
1
=
m
^
N
–
1
+
L
2
+
1
,
where {circumflex over (m)}N\u22121=arg maxmsmN\u22121 and smN\u22121=\u03a3i=0L|Ci+mN\u22121|.
13. The system of claim 10, wherein the instructions for determining the initial side track pulse shape include instructions for using a correlation metric CmN\u22121=\u03a3k=1TykNbk\u2212mN\u22121, where T is a number of samples used for the correlation.
14. The system of claim 10, wherein the instructions for determining the initial phase offset include instructions for using
L
^
N
–
1
=
L
max
2
+
1
–
i
max
,
where imax=arg maxi\u0125iLMSN\u22121 and Lmax is the length of the initial side track pulse shape.
15. The system of claim 10, wherein the instructions for determining the initial side track pulse shape include instructions for using \u0125LMSN\u22121=arg min hN\u22121E|ek1|2, where ek1=ykN\u2212\u03a3i=\u2212LmaxLmaxhiN\u22121bk\u2212iN\u22121 and Lmax is the length of the initial side track pulse shape.
16. The system of claim 10, wherein the instructions for determining the initial side track pulse shape include instructions for using \u0125k+1LMSN\u22121= \u0125kLMSN\u22121+\u03bc1\xd7ek1\xd7 bkN\u22121, where ek1=ykN\u2212\u03a3i=\u2212LmaxLmaxhiN\u22121bk\u2212iN\u22121, Lmax is the length of the initial side track pulse shape, \u03bc1 is an adaptation coefficient, and bKN\u22121=bk\u2212LmaxN\u22121 . . . bk+LmaxN\u22121.
17. The system of claim 10, wherein the memory is further configured to provide the processor with instructions which when executed cause the processor to:
determine a second side track pulse shape, using the initial side track pulse shape and the side track interference, wherein the second side track pulse shape minimizes the contribution of the side track interference to a second center track bit; and
remove the contribution of the side track interference from the second center track bit using the second side track pulse shape and side track data.
18. The system of claim 17, wherein using the processor to determine the second side track pulse shape includes using \u0125k+1LMSN\u22121= \u0125kLMSN\u22121+\u03bc5\xd7ek5\xd7 bkN\u22121, where ek5=ykN\u2212\u03a3i=\u2212LLhiN\u22121bk\u2212i\u2212{circumflex over (L)}N\u22121N\u22121 and \u03bc5 is an adaptation coefficient.
19. A computer program product, the computer program product being embodied in a tangible computer readable storage medium and comprising computer instructions for:
determining an initial phase offset between a center track and a side track;
using a processor to determine an initial side track pulse shape, using the initial phase offset and side track interference, wherein the initial side track pulse shape minimizes a contribution of the side track interference to a center track bit; and
removing the contribution of the side track interference from the center track bit using the initial side track pulse shape and the side track interference.
20. The computer program product of claim 19, wherein the center track and the side track are associated with a shingled magnetic recording (SMR) system.