1. A process for the conversion of lignin to substituted phenolic compounds, said process comprising the steps of:
i. charging lignin and a catalyst in the ratio ranging between 0.1:1 to 1:0.1 into a reactor followed by charging a solvent, wherein the catalyst consists of a heterogeneous solid acid catalyst;
ii. optionally flushing the reactor with nitrogen, argon, helium, hydrogen or air;
iii. adjusting the reactor to operate at atmospheric pressure and heating the reactor to a temperature in the range of 50 to 300\xb0 C. with stirring;
iv. raising the stirring speed to 10 to 2000 rpm after stabilizing at the temperature; and
v. carrying out a reaction for a period in the range of 0.1 to 96 hours to obtain substituted phenolic compounds.
2. The process as claimed in claim 1, wherein the heterogeneous solid acid catalyst is selected from the group consisting of zeolite, clays, metal oxides, mixed metal oxides, supported metal oxides, acid treated oxides.
3. The process as claimed in claim 1, wherein the solvent is selected from the group consisting of organic solvent or a mixture of water and organic solvent in a ratio of 1:99 to 99:1 and said organic solvent is selected from the group consisting of alcohols, esters, hexane, acids, toluene and xylene.
4. The process as claimed in claim 1, wherein said catalyst is recyclable and reusable.
5. The process as claimed in claim 1, wherein the substituted phenolic monomer compounds are represented by general formula 1
wherein,
R1=\u2014H, \u2014OH, \u2014OCH3, \u2014OCH2\u2014CH3, \u2014CH\u2550CH2, \u2014CH\u2550CH\u2014CH3,
R2=\u2014H, \u2014OH, \u2014OCH3, \u2014OCH2\u2014CH3, \u2014CH\u2550CH2, \u2014CH\u2550CH\u2014CH3, \u2014CO\u2014CH3, \u2014CO\u2014CH\u2550CH2, \u2014CH2\u2014CH3, \u2014CH2\u2014CH2\u2014CH3, \u2014CHO, \u2014CHOH\u2014CHOH\u2014CH3, \u2014CHOH\u2014CO\u2014CH2OH, \u2014C(CH3)3;
R3=\u2014H, \u2014OH, \u2014OCH3, \u2014OCH2\u2014CH3, \u2014CH\u2550CH2, \u2014CH\u2550CH\u2014CH3, \u2014CO\u2014CH3, \u2014CO\u2014CH\u2550CH2, \u2014CH2\u2014CH3, \u2014CH2\u2014CH2\u2014CH3, \u2014CHO, \u2014CH2\u2014CO\u2014CH3, \u2014CH2OH, \u2014CH2\u2014CH2OH, \u2014CO\u2014OCH3\u2014CH2\u2014COOH, \u2014CH\u2550CH\u2014CHO, \u2014CH\u2550CH\u2014COOH, \u2014CH2\u2014CH2\u2014CH2\u2014CH3, -PhAr, \u2014O-PhAr;
R4=\u2014H, \u2014OH, \u2014OCH3, \u2014OCH2\u2014CH3, \u2014CH\u2550CH2, \u2014CH\u2550CH\u2014CH3, \u2014CO\u2014CH3, \u2014CH2\u2014CH3, \u2014CHO, CH2\u2014CH2\u2014CH3, \u2014CH2\u2014CH2OH, \u2014CH2OH, \u2014CH\u2550CH\u2014OH, \u2014CH\u2550CH\u2014CH2OH, CH2\u2014CO\u2014CH3, \u2014COOH, \u2014CH2\u2014COOH, \u2014CH\u2550CH\u2014CHO, \u2014CH\u2550CH\u2014COOH, \u2014CH2\u2014CH2\u2014CH2\u2014CH3, \u2014OCH2R1, -PhAr, \u2014O-PhAr.
6. The process as claimed in claim 1, wherein said process is conducted in batch mode.
7. The process as claimed in claim 1, wherein said process is conducted in continuous mode.
8. The process as claimed in claim 1, wherein the temperature is below 270\xb0 C.
9. The process as claimed in claim 1, further comprising the steps of:
vi. recovering the substituted phenolic compounds; and
vii. recovering the catalyst.
10. The process as claimed in claim 9, wherein the process consists essentially of steps (i), (iii), (iv), (v), (vi), and (vii), and optionally step (ii).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs), comprising:
identifying a plurality of components to duplicate in response to slack values associated with connections to the components in placement locations and adding duplication moves for the plurality of components to a queue;
identifying a single component to duplicate in response to slack values associated with connections to the component in placement locations and adding duplication moves for the component to the queue; and
prioritizing queue entries such that the plurality of components are duplicated before the single component.
2. The method of claim 1, wherein the duplicated components are implemented by logic elements (LE) on a same logic array block (LAB) on the target device.
3. The method of claim 1, further comprising:
synthesizing a design for the system;
mapping components in the design onto resources on the target device; and
determining the placement locations for the components on the target device.
4. The method of claim 1, further comprising routing of the system to provide interconnections to the plurality of components that are duplicated.
5. The method of claim 1, wherein identifying the plurality of components to duplicate comprises identifying a candidate chain of logic elements to duplicate.
6. The method of claim 5, wherein identifying the candidate chain comprises identifying a first logic element that is a non-registered logic element that feeds a registered logic element in a different logic array block (LAB).
7. The method of claim 6, further comprising identifying logic elements that drive the first logic element and that reside in a same LAB.
8. The method of claim 5, further comprising determining whether duplicating the plurality of components exceeds a threshold number of duplications.
9. The method of claim 5, further comprising determining whether resources exist to support duplication of the chain of logic elements.
10. The method of claim 5, further comprising determining whether the duplication improves slack on the target device.
11. A machine-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform:
identifying a plurality of components to duplicate in response to slack values associated with connections to the components in placement locations and adding duplication moves for the components to a queue;
identifying a single component to duplicate in response to slack values associated with connections to the component in placement locations and adding duplication moves for the component to the queue; and
prioritizing queue entries such that the plurality of components are duplicated before the single component.
12. The machine-readable medium of claim 11, wherein the duplicated components are implemented by logic elements (LE) on a same logic array block (LAB) on the target device.
13. The machine-readable medium of claim 11, wherein identifying the plurality of components to duplicate comprises identifying a candidate chain of logic elements to duplicate.
14. The machine-readable medium of claim 13, wherein identifying the candidate chain comprises identifying a first logic element that is a non-registered logic element that feeds a registered logic element in a different logic array block (LAB).
15. The machine-readable medium of claim 14, further comprising instructions which when executed by the processor, causes the processor to perform identifying logic elements that drive the first logic element and that reside in a same LAB.
16. The machine-readable medium of claim 13, further comprising instructions which when executed by the processor, causes the processor to perform further comprising determining whether the duplication improves slack on the target device.
17. A compound duplication unit, comprising:
a candidate chain identifier to identify a plurality of components to duplicate in response to slack values associated with connections to the components in placement locations and adding duplication moves for the components in a queue and to identify a single component to duplicate in response to slack values associated with connections to the component in placement locations and adding duplication moves for the component to the queue; and
a duplication manager to prioritize queue entries such that the plurality of components are duplicated before the single component.
18. The apparatus of claim 17, wherein the plurality of components to duplicate are to be implemented by logic elements (LE) on a same logic array block (LAB) on the target device.
19. The apparatus of claim 17, wherein the candidate chain identifier identifies a first logic element that is a non-registered logic element that feeds a registered logic element in a different logic array block (LAB).
20. The apparatus of claim 19, wherein the candidate chain identifier identifies logic elements that drive the first logic element and that reside in a seine LAB.
21. The apparatus of claim 17, further comprising a duplication checker to determine whether resources exist to support duplication of the chain of logic elements.
22. The apparatus of claim 17, further comprising a slack evaluator to determine whether the duplication improves slack on the target device.