1. An analog-to-digital (A-D) converter, which converts an analog signal to a digital signal of a predetermined bit number a plurality of times, the A-D converter comprising:
an A-D conversion circuit which samples an inputted analog signal and converts it to a digital value of a bit number less than the predetermined bit number;
a first holding circuit which holds the inputted analog signal; and
a buffer circuit provided on a path connecting an input side of said A-D conversion circuit with an input side of said first holding circuit.
2. An analog-to-digital converter according to claim 1, wherein said buffer circuit is a source follower circuit.
3. An analog-to-digital converter according to claim 1, further comprising a digital-to-analog (D-A) conversion circuit which converts an output signal of said A-D conversion circuit to an analog signal,
wherein said first holding circuit subtracts the output signal of said D-A conversion circuit from the analog signal held, and amplifies a signal, obtained as a result of the subtraction, by a predetermined gain.
4. An analog-to-digital converter according to claim 1, further comprising:
a plurality of second holding circuits which sample and hold a plurality of analog signals to be inputted, respectively; and
a signal selector which selects any of outputs of the plurality of second holding circuits and which outputs a selected output to said A-D conversion circuit and said first holding circuit.
5. An analog-to-digital converter according to claim 4, wherein the respective plurality of second holding circuits output, in a branched manner, the analog signal held to a path for use with said A-D conversion circuit and a path for use with said first holding circuit, and
wherein said buffer circuit is provided on the path for use with said A-D conversion circuit.
6. An analog-to-digital converter according to claim 5, wherein said buffer circuit is provided on the path for use with said first holding circuit, in addition to the path for use with said A-D conversion circuit.
7. An analog-to-digital converter according to claim 6, wherein each of the plurality of second holding circuits includes:
a differential amplifier circuit which receives the analog signal to be inputted;
a feedback buffer circuit and a first capacitor which are connected in series between an output terminal of the differential amplifier circuit and an input terminal of the differential amplifier terminal and
a second capacitor provided on a path through which the analog signal to be inputted is led to the input terminal of the differential amplifier circuit,
wherein an output signal of the differential amplifier circuit is outputted, in a branched manner, to a path for use with said A-D conversion circuit and a path for use with said first holding circuit.
8. An analog-to-digital converter according to claim 6, wherein power supply voltage of a circuit element placed posterior to said buffer circuit when viewed from an input side of the analog signal is less than that of said buffer circuit and a circuit element placed anterior thereto.
9. An analog-to-digital converter according to claim 8, wherein said buffer circuit functions as a voltage converter circuit that steps down the inputted analog signal by a predetermined level.
10. An analog-to-digital (A-D) converter, which converts an analog signal to a digital signal a plurality of times, the A-D converter comprising:
a predetermined circuit element which outputs an analog signal;
an A-D conversion circuit which samples the analog signal outputted from said predetermined circuit element and converts it to a digital value of a predetermined bit number less than a targeted bit number; and
a first holding circuit, provided in parallel with said A-D conversion circuit, which at least holds the analog signal sampled by said A-D conversion circuit,
wherein a buffer circuit for said first holding circuit and a buffer circuit for said A-D conversion circuit are separately provided at an output side of said predetermined circuit element.
11. An analog-to-digital converter according to claim 10, wherein power supply voltage of a circuit element placed posterior to the buffer circuit for said first holding circuit and the buffer circuit for said A-D when viewed from an input side of the analog signal is less than that of the buffer circuit for said first holding circuit, the buffer circuit for said A-D and a circuit element placed anterior thereto.
12. An analog-to-digital converter according to claim 10, wherein said predetermined circuit element is a sample-and-hold circuit.
13. An analog-to-digital converter according to claim 10, wherein the buffer circuit for said first holding circuit is provided on a path connecting said predetermined circuit element with said first holding circuit, and the buffer circuit for said A-D conversion circuit is provided on a path connecting a connection point of said predetermined circuit element and the buffer circuit for said first holding circuit with said A-D conversion circuit.
14. An analog-to-digital converter according to claim 1, wherein said A-D conversion circuit receives the analog signal at one end of a capacitance connected to the input side thereof, and includes a voltage comparison element of capacitive coupling input type that samples the analog signal appearing at the other end of the capacitance.
15. An analog-to-digital converter according to claim 1, wherein said first holding circuit and said A-D conversion circuit are included in a block where the analog signal is first converted to the digital value.
16. An analog-to-digital converter according to claim 1, further comprising:
a D-A conversion circuit which converts an output signal of said A-D conversion circuit to an analog signal; and
a subtracter circuit which subtracts the output signal of said D-A conversion circuit from an output signal of said first holding circuit,
wherein, during a holding period, said first holding circuit amplifies the sampled analog signal by a predetermined gain, and
wherein said subtracter circuit subtracts the output signal of said D-A conversion circuit amplified at the same predetermined gain.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing an integrated device and a test structure for characterizing properties of the integrated device, the method comprising:
(a) manufacturing the integrated device comprising (i) a substrate, (ii) a pad having a periphery, the pad overlying the substrate to form a pad-substrate interface, (iii) a solder mask overlying the substrate, the solder mask having an opening with a periphery, wherein the periphery of the pad is within the periphery of the opening, and (iv) a solder bump attached to the pad to form a solder-pad interface; and
(b) manufacturing the test structure comprising (i) a substrate, (ii) a pad corresponding to the pad of the integrated device and having a periphery, the pad overlying the substrate to form a pad-substrate interface, (iii) a solder mask overlying the substrate, the solder mask having an opening with a periphery, wherein the periphery of the pad extends below the solder mask and beyond the periphery of the opening, and (iv) a solder bump attached to the pad, wherein:
extending the periphery of the pad of the test structure below the solder mask and beyond the periphery of the opening strengthens the pad-substrate interface of the pad of the test structure compared to the pad-substrate interface of the pad of integrated device; and
the integrated device and the test structure are part of a single manufacturing lot.
2. The method of claim 1, further comprising:
(c) performing testing on the solder bump of the test device to characterize properties of the solder-pad interface of the integrated device.
3. The method of claim 2, wherein the testing includes stress testing.