1. A semiconductor device comprising:
a wiring board having an upper surface, a plurality of first bonding leads formed along a first upper surface side of the upper surface, a plurality of second bonding leads formed along a second upper surface side facing to the first upper surface side of the upper surface, a lower surface opposite to the upper surface, and a plurality of bump lands formed on the lower surface, a shape in a plan view of the upper surface being comprised of a quadrangle;
a first semiconductor chip having a main surface, a plurality of first main surface side pads formed along a first main surface side of the main surface, a plurality of second main surface side pads formed along a second main surface side facing to the first main surface side of the main surface, and a rear surface opposite to the main surface, and mounted on the upper surface of the wiring board such that the rear surface faces to the upper surface of the wiring board, and such that the first and second main surface sides, are aligned with the first and second upper surface sides, respectively, in the plan view, and such that each of the first bonding leads and the second boding leads is exposed, a shape in a plan view of the main surface being comprised of a quadrangle;
a second semiconductor chip having a front surface, a plurality of first front surface side pads formed along a first front surface side of the front surface, and a back surface opposite to the front surface, and mounted on the main surface of the first semiconductor chip such that the back surface faces to the main surface of the first semiconductor chip, and such that the first and second front surface sides are aligned with the first and second main surface sides, respectively, in the plan view, and such that each of the first main surface side pads and the second main surface side pads is exposed, a shape in a plan view of the front surface being comprised of a quadrangle;
a plurality of first wires electrically connected the first main surface side pads with a first lead group of the first bonding leads, respectively;
a plurality of second wires electrically connected the second main surface side pads with the second bonding leads, respectively, and
a plurality of third wires electrically connected the first front surface side pads with a second lead group of the first bonding leads, respectively,
wherein the first semiconductor chip performs interface control of high-frequency contactless communication and data processing of communications data, and
wherein the second semiconductor chip performs another data processing of the communication data, and
wherein the first main surface side pads include a plurality of first pads each for externally outputting a high-frequency transmission current signal and a plurality of second pads each for inputting a high-frequency receiving current signal from the outside, and
wherein the first pads are arranged closer to the second main surface side than the other pads of the first main surface side pads.
2. The semiconductor device according to claim 1,
wherein the first pads and the second pads are used in connection with an antenna for electromagnetic wave communication.
3. The semiconductor device according to claim 2,
wherein an output transistor to be connected with the first pads has a size larger than that of an input transistor to be connected with the second pads.
4. The semiconductor device according to claim 1,
wherein the second semiconductor chip is mounted on the main surface of the first semiconductor chip by being biased, along the first main surface side of the first semiconductor chip, in a direction away from the first pads.
5. The semiconductor device according to claim 4,
wherein the second lead group are arranged, along the first upper surface side, by being biased in a direction in which the second semiconductor chip is biased, and
wherein the first front surface side pads are arranged, along the first front surface side, by being biased in the direction in which the second semiconductor chip is biased.
6. The semiconductor device according to claim 1,
wherein communication signals of the high-frequency contactless communication to be processed by the first semiconductor chip are ones of the first to third ASK modulation modes, the carrier frequencies of which are equal to each other, and a signal of the second ASK modulation mode has a modulation depth lower than that of a signal of the first ASK modulation mode and has a communication speed equal to that of a signal of the first ASK modulation mode, and a signal of the third ASK modulation mode has a modulation depth lower than that of a signal of the first ASK modulation mode and has a communication speed higher than that of a signal of the first ASK modulation mode, and
wherein the first semiconductor chip performs both interface control of the high-frequency contactless communication, and as the data processing, secure processing on received data and transmission data of the first and second ASK modulation modes, and
wherein the second semiconductor chip performs, as the another data processing, secure processing on received data and transmission data of the third ASK modulation mode.
7. A method of manufacturing a semiconductor device comprising the following steps of:
(a) providing a wiring board having an upper surface, a plurality of first bonding leads formed along a first upper surface side of the upper surface, a plurality of second bonding leads formed along a second upper surface side facing to the first upper surface side of the upper surface, a lower surface opposite to the upper surface, and a plurality of bump lands formed on the lower surface, a shape in a plan view of the upper surface being comprised of a quadrangle;
(b) after the step (a), mounting a first semiconductor chip on the upper surface of the wiring board, the first semiconductor chip having a main surface, a plurality of first main surface side pads formed along a first main surface side of the main surface, a plurality of second main surface side pads formed along a second main surface side facing to the first main surface side of the main surface, and a rear surface opposite to the main surface, and performing both interface control of high-frequency contactless communication and data processing of communication data, and the first semiconductor chip being mounted such that the rear surface of the first semiconductor chip faces to the upper surface of the wiring board, and such that the first and second main surface sides are aligned with the first and second upper surface sides, respectively, in the plan view, and such that each of the first bonding leads and the second boding leads is exposed from the first semiconductor chip, a shape in a plan view of the main surface being comprised of a quadrangle;
(c) after the step (b), mounting a second semiconductor chip on the main surface of the first semiconductor chip, the second semiconductor chip having a front surface, a plurality of first front surface side pads formed along a first front surface side of the front surface, and a back surface opposite to the front surface, and performing another data processing of the communication data, and the second semiconductor chip being mounted such that the back surface faces to the main surface of the first semiconductor chip, and such that the first front surface side is aligned with the first main surface side, respectively, in the plan view, and such that each of the first main surface side pads and the second main surface side pads is exposed, a shape in a plan view of the front surface being comprised of a quadrangle; and
(d) after the step (c), electrically connecting the first main surface side pads with a first lead group of the first bonding leads via a plurality of first wires, the second main surface side pads with the second bonding leads via a plurality of second wires, and the first front surface side pads and a second lead group of the first bonding leads via a plurality of third wires,
wherein the first main surface side pads in the first semiconductor chip include both a plurality of first pads each for externally outputting a high-frequency transmission current signal and a plurality of second pads each for inputting a high-frequency receiving current signal from the outside, and
wherein the first pads are arranged closer to the second main surface side than the other pads of the first main surface side pads.
8. The method of manufacturing a semiconductor device according to claim 7,
wherein the first pads and the second pads are used in connection with an antenna for electromagnetic wave communication.
9. The method of manufacturing a semiconductor device according to claim 8,
wherein an output transistor to be connected with the first pads has a size larger than that of an input transistor to be connected with the second pads.
10. The method of manufacturing a semiconductor device according to claim 7,
wherein in the step (c), the second semiconductor chip is mounted on the main surface of the first semiconductor chip by being biased, along the first main surface side of the first semiconductor chip, in a direction away from the first pads.
11. The method of manufacturing a semiconductor device according to claim 10,
wherein the second lead group are arranged, along the first upper surface side, by being biased in a direction in which the second semiconductor chip is biased, and
wherein the first front surface side pads are arranged, along the first front surface side, by being biased in the direction in which the second semiconductor chip is biased.
12. The method of manufacturing a semiconductor device according to claim 7,
wherein communication signals of the high-frequency contactless communication to be processed by the first semiconductor chip are ones of the first to third ASK modulation modes, the carrier frequencies of which are equal to each other, and a signal of the second ASK modulation mode has a modulation depth lower than that of a signal of the first ASK modulation mode and has a communication speed equal to that of a signal of the first ASK modulation mode, and a signal of the third ASK modulation mode has a modulation depth lower than that of a signal of the first ASK modulation mode and has a communication speed higher than that of a signal of the first ASK modulation mode, and
wherein the first semiconductor chip performs both interface control of the high-frequency contactless communication, and as the data processing, secure processing on received data and transmission data of the first and second ASK modulation modes, and
wherein the second semiconductor chip performs, as the another data processing, secure processing on received data and transmission data of the third ASK modulation mode.
13. A semiconductor device comprising:
a wiring board having a plurality of bonding leads along one periphery thereof;
a first semiconductor chip that has a plurality of pads along one periphery adjacent to the one periphery of the wiring board, and that is mounted on the wiring board such that each of the bonding leads is exposed, and that performs both interface control of high-frequency contactless communication and data processing of communication data; and
a second semiconductor chip that has a plurality of pads along one periphery adjacent to the one periphery of the first semiconductor chip, and that is mounted on the first semiconductor chip such that each of the pads in first semiconductor chip is exposed, and that performs another data processing of the communication data,
wherein the pads in the first semiconductor chip and a first lead group of the bonding leads are respectively and electrically connected by a plurality of first wires, and
wherein the pads in the second semiconductor chip and a second lead group of the bonding leads are respectively and electrically connected by a plurality of second wires, and
wherein the pads in the first semiconductor chip include a plurality of first pads each for externally outputting a high-frequency transmission current signal and a plurality of second pads each for inputting a high-frequency receiving current signal from the outside, and
wherein of the pads in the first semiconductor chip, the first pads are arranged at positions farther from the one periphery of the first semiconductor chip than those of the other pads, and
wherein the second semiconductor chip is mounted on the first semiconductor chip by being biased, along the one periphery of the first semiconductor chip, in a direction away from the first pads.
14. The semiconductor device according to claim 13,
wherein the second lead group are arranged, along the one periphery of the wiring board, by being biased in a direction in which the second semiconductor chip is biased, and
wherein the pads in the second semiconductor chip are arranged, along the one periphery, by being biased in the direction in which the second semiconductor chip is biased.
15. The semiconductor device according to claim 13,
wherein communication signals of the high-frequency contactless communication to be processed by the first semiconductor chip are ones of the first to third ASK modulation modes, the carrier frequencies of which are equal to each other, and a signal of the second ASK modulation mode has a modulation depth lower than that of signal of the first ASK modulation mode and has a communication speed equal to that of a signal of the first ASK modulation mode, and a signal of the third ASK modulation mode has a modulation depth lower than that of a signal of the first ASK modulation mode and has a communication speed higher than that of a signal of the first ASK modulation mode, and
wherein the first semiconductor chip performs both interface control of the high-frequency contactless communication, and as the data processing, secure processing on received data and transmission data of the first and second ASK modulation modes, and
wherein the second semiconductor chip performs, as the another data processing, secure processing on, received data and transmission data of the third ASK modulation mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A crystallized glass containing, as a main crystal phase, one or more selected from RAl2O4 and R2TiO4 (wherein R is one or more selected from Mg and Fe),
the crystallized glass comprising, in terms of mass percentage On an oxide basis,
SiO2 of 50% to 70%,
Al2O3 of 10% to 26%,
TiO2 of 1 to 15%,
MgO of 2.5% to 25%,
FeO of 0% to 8%,
ZnO of 0% to less than 2%, and
R\u20322O component of 1 to 15% (wherein R\u2032 is one or more selected from Li, Na, and K),
wherein the value of (Al2O3 +MgO)SiO2 is 0.30 or more and 0.65 or less, and a specific gravity is less than 2.63.
2. The crystallized glass according to claim 1, wherein the total of the components of CaO, SrO, BaO, and Y2O3 is 1% or less, expressed in terms of mass percentage on an oxide basis.
3. The crystallized glass according to claim 1, wherein the ZrO2 component is contained in the amount of 0% to 1.9%, expressed in terms of mass percentage on an oxide basis.
4. The crystallized glass according to claim 1, further comprising the components of
Al2O3 of 12.8% to 26%,
MgO of 2.5% to 15%, and
TiO2 of 1 to 11%, expressed in terms of mass percentage on an oxide basis,
wherein the value of (Al2O3+MgO)SiO2 is 0.30 or more and 0.62 or less.
5. The crystallized glass according to claim 1, further comprising the components of
CaO of 0% to 1%,
SrO of 0% to 1%,
BaO of 0% to 1%,
P2O5 of 0% to 7%,
B2O3 of 0% to 12%, and
Y2O3 of 0% to 1%, expressed in terms of mass percentage on an oxide basis.
6. A crystallized glass substrate for information recording medium, using the crystallized glass according to claim 1.
7. The crystallized glass substrate for information recording medium according to claim 6, wherein a compression stress layer is formed at one or both of an outer periphery edge and an inner periphery edge of the crystallized glass substrate.
8. The crystallized glass substrate for information recording medium according to claim 6, wherein a compression stress layer is formed at one or both of two main surfaces of the crystallized glass substrate, and the thickness of the compression stress layer is less than 30 \u03bcm.
9. An information recording medium, using the crystallized glass substrate according to claim 6.