1. A method comprising;
counting a number of process cycles performed on a first memory block in a memory device; and
adjusting a difference between a program verify voltage and a read voltage associated with the number of process cycles, from an initial voltage difference, in response to the counted number of process cycles.
2. The method of claim 1, wherein adjusting a difference between a program verify voltage and a read voltage includes increasing the difference from the initial voltage difference as the number of process cycles for the memory block increases.
3. The method of claim 1, wherein the method includes increasing the read voltage from an initial read voltage value in response to the counted number of process cycles.
4. The method of claim 1, wherein adjusting a difference between a program verify voltage and a read voltage includes increasing the difference from the initial voltage difference periodically as the number of process cycles for the memory block increases past a number of process cycle count thresholds.
5. The method of claim 4, wherein increasing the difference from the initial voltage difference includes increasing the difference by about 100 mV.
6. The method of claim 1, wherein counting a number of processing cycles performed on a first memory block includes counting a number of programerase cycles performed on the memory block, and wherein the memory device includes a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines.
7. The method of claim 1, wherein the initial voltage difference is in the range of 100-200 mV.
8. The method of claim 1, wherein the memory device is a flash memory device, and wherein the memory block comprises multiple level memory cells (MLCs).
9. A method comprising;
counting a number of programerase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of multiple level memory cells (MLCs) arranged in rows that are coupled by word lines, and each MLC capable of being programmed to an erased level and capable of being programmed to at least a first program level and a second program level, the second program level being higher than the first; and
adjusting a difference between a program verify voltage and a corresponding read voltage associated with at least one of the first program level and second program level of at least one of the plurality of MLCs, from an initial voltage difference, in response to the counted number of programerase cycles.
10. The method of claim 9, wherein each of the program levels has a different program verify voltage and read voltage associated therewith, and wherein adjusting a difference between a program verify voltage and a corresponding read voltage includes adjusting the difference between the program verify voltage and corresponding read voltage associated with each one of the program levels of at least one of the plurality of MLCs, from an initial voltage difference, in response to the counted number of programerase cycles.
11. The method of claim 9, wherein adjusting a difference between a program verify voltage and a corresponding read voltage associated with at least one of the first program level and second program level of at least one of the plurality of MLCs includes increasing the difference, from the initial voltage difference, when the counted number of programerase cycles reaches a threshold value.
12. The method of claim 11, wherein increasing the difference, from the initial voltage difference, includes increasing the difference associated with the first program level at a threshold value that is different than a threshold value at which the difference associated with the second program level is increased.
13. The method of claim 11, wherein the second program level corresponds to a higher state of the MLC than the first program level and increasing the difference, from the initial voltage difference, includes increasing the difference associated with the second program level by a greater amount than the first program level.
14. The method of claim 13, wherein the initial voltage difference associated with the first program level is in the range of 0.1-0.15V and the initial voltage difference associated with the second program level is in the range of 0.16-0.3V, and wherein increasing the difference associated with the second level includes increasing the difference by about 0.5V.
15. A non-volatile memory device comprising:
an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming the array that includes:
generating an initial program verify voltage;
generating an initial read voltage;
counting a quantity of programerase cycles performed on the array; and
increasing a difference between the initial program verify voltage and the initial read voltage based upon the quantity of programerase cycles.
16. The device of claim 15, wherein the control circuitry is programmed to increase the difference each time the counted quantity reaches a predetermined value of programerase cycles.
17. The device of claim 15, wherein the control circuitry is programmed to increase the difference by a particular voltage amount each time the counted quantity reaches 1,000 programerase cycles.
18. The device of claim 15, wherein the control circuitry is programmed to increase the initial read voltage based upon the quantity of programerase cycles.
19. The device of claim 15, wherein the non-volatile memory cells are multiple level cells (MLCs) having a plurality of program states, and wherein the control circuitry is programmed to:
generate an initial program verify voltage for each of the plurality of program states;
generate an initial read voltage for each of the plurality of program states; and
increase a difference between the initial program verify voltage and the initial read voltage of each of the plurality of program states.
20. The device of claim 19, wherein the control circuitry is programmed to increase a difference between the initial program verify and read voltage of a first program state by an amount different from an increase in a difference between the initial program verify and read voltage of a second program state.
21. The device of claim 19, wherein the control circuitry is programmed to:
increase a difference between the initial program verify and read voltage of a first program state after a first quantity of programerase cycles; and
increase a difference between the initial program verify and read voltage of a second program state after a second quantity of programerase cycles.
22. The device of claim 15, wherein the array of non-volatile memory cells is arranged in a NAND architecture.
23. A memory system comprising:
a processor for generating memory control signals;
a flash memory device coupled to the processor, the device comprising;
a memory cell array arranged in rows and columns; and
control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation wherein the control circuitry is adapted to adjust a difference between at least one of the number program verify voltages and at least one of the number of read voltages, from an initial voltage difference to an adjusted voltage difference based on a count of processing cycles performed on the array.
24. The system of claim 23, wherein the control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation is adapted to increase the difference between at least one of the number program verify voltages and at least one of the number of read voltages, from the initial voltage difference to the adjusted voltage difference based on a count of programmingerase cycles performed on the array.
25. A memory module comprising:
a memory device comprising:
a memory cell array arranged in rows and columns;
control circuitry for controlling a number of program verify voltages and a number of read voltages during a program operation wherein the control circuitry is adapted to increase a difference between at least one of the number program verify voltages and at least one of the number of read voltages, from an initial voltage difference to an adjusted voltage difference based on a count of programerase cycles performed on the array; and
a plurality of contacts configured to provide selective contact between the memory device and a host system.
26. The module of claim 25, and further including a memory controller coupled to the memory device for controlling operation of the memory device in response to the host system.
27. The module of claim 25, wherein the plurality of non-volatile memory cells are flash memory cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for generating a Service-Oriented Architecture (SOA) policy based on a context model, comprising:
generating, by a computer hardware system, an application scope of the SOA policy;
generating, by the computer hardware system, the context model by
collecting SOA metadata documents compliant with the application scope of the SOA policy,
establishing inter-document references among the SOA metadata documents, and
aggregating the SOA metadata documents based on the inter-document references to generate the context model;
generating, by the computer hardware system, an action list for the context model based on action semantic modules customized by a user;
generating, by the computer hardware system, a condition part of the SOA policy;
generating, by the computer hardware system, an action part of the SOA policy according to the action list; and
combining, by the computer hardware system, the condition part and the action part of the SOA policy to generate the SOA policy wherein
the inter-document references causes the SOA metadata documents to be mutually referenced.
2. The method of claim 1, wherein
the application scope includes at least one of: a policy type or a policy application scenario.
3. The method of claim 1, wherein
the generating the action list for the context model includes:
obtaining the action semantic modules customized by the user and their XML description files;
reading the XML description files; and
introducing the action semantic modules into the action list according to the XML description files.
4. The method of claim 1, wherein
the generating the condition part of the SOA policy includes:
extracting condition terms and their relations from the SOA metadata documents in the context model;
displaying the condition terms; and
selecting the condition terms and operators to generate the condition part.
5. The method of claim 1, wherein
the generating the action part of the SOA policy according to the action list includes:
displaying the action semantic modules in the action list;
selecting required action semantic modules; and
setting parameters in the required action semantic modules.
6. The method according to claim 1, further comprising
generating a context model template including the context model and the SOA metadata documents.
7. The method of claim 6, further comprising
registering the context model template and the SOA policy with a policy manager.
8. A computer hardware apparatus for generating a Service-Oriented Architecture (SOA) policy based on a context model, comprising:
an application scope generating module configured to generate an application scope of the SOA policy;
a processor configured to generate the context model for generating a Service-Oriented Architecture (SOA) policy, the processor including:
a collector configured to collect SOA metadata documents compliant with the application scope of the SOA policy;
an inter-document reference establishing module configured to establish inter-document references among the SOA metadata documents; and
an aggregator configured to aggregate the SOA metadata documents according to the inter-document references to generate a context model;
an action list generator configured to generate an action list for the context model based on action semantic modules customized by a user;
a condition generator configured to generate a condition part of the SOA policy;
an action generator configured to generate an action part of the SOA policy according to the action list; and
a policy generator configured to combine the condition part and the action part to generate the SOA policy wherein
the inter-document references causes the SOA metadata documents to be mutually referenced.
9. The computer hardware apparatus of claim 8, wherein
the action list generator includes:
an obtaining unit configured to obtain the action semantic modules customized by the user and the user’s XML description files;
a reading unit configured to read the XML description files; and
an introducing unit configured to introduce the action semantic modules into the action list according to the XML description files.
10. The computer hardware apparatus of claim 8, wherein
the condition generator includes:
an extracting unit configured to extract condition terms from the SOA metadata documents in the context model;
a condition term displaying unit configured to display the condition terms; and
a selecting unit configured to select the condition terms and operators to generate the condition part.
11. The computer hardware apparatus of claim 8, wherein
the action generator comprises:
a module displaying unit configured to display the action semantic modules in the action list;
a module selecting unit configured to select required action semantic modules; and
a parameter setting unit configured to set parameters in the action semantic modules.
12. The computer hardware apparatus of claim 8, further comprising
a template generator configured to generate a context model template including the context model and the SOA metadata documents.