1. An integrated circuit comprising:
a plurality of active areas formed in a semiconductor substrate with a substrate surface, each active area having two lateral sides extending along a first direction with rows of active areas being separated from each other by isolation grooves, wherein each active area includes a first sourcedrain region formed adjacent the substrate surface, a second sourcedrain region formed adjacent the substrate surface, and a channel region separating the first and second sourcedrain regions, each of the first and second sourcedrain regions being distanced from and oriented with respect to each other along the first direction; and
gate electrodes disposed along the channel regions and being electrically isolated from the channel regions by gate isolating layers; and
a plurality of sets of first and second word lines disposed on opposing lateral sides of each of the rows of active areas and with each of the first and second word lines including a length that extends along the first direction, wherein the first and second word lines of each set are connected with each other via the gate electrodes of a corresponding row of active areas.
2. The integrated circuit according to claim 1, wherein each of the gate electrodes has a top side, the top side of the gate electrode being disposed beneath the surface of the semiconductor substrate.
3. The integrated circuit according to claim 1, wherein each channel region includes a fin-region in which the channel region has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second sourcedrain regions, and wherein the gate electrode is disposed at three sides of the ridge.
4. The integrated circuit according to claim 2, wherein each channel region includes a fin-region in which the channel region has the shape of a ridge, the ridge includes a top side and two lateral sides in a cross section perpendicular to a line connecting the first and second sourcedrain regions, and wherein the gate electrode is disposed at three sides of the ridge.
5. The integrated circuit according to claim 1, wherein two word lines are disposed in each of the isolation grooves, the two word lines being isolated from each other and being assigned to two different rows of active areas.
6. The integrated circuit according to claim 1, further comprising a storage capacitor connected with a first sourcedrain region, wherein the storage capacitor is a stacked capacitor.
7. The integrated circuit according to claim 1, further comprising a plurality of memory cells, each memory cell comprising a storage capacitor, wherein an active area, a gate electrode, and the memory cells are arranged in rows and columns, respectively, and the memory cells are further arranged in the form of a regular grid.
8. The integrated circuit according to claim 1, wherein each gate electrode has a bottom side, each of the first and second sourcedrain regions extending to a depth below or equal to the bottom side of the gate electrode.
9. The integrated circuit according to claim 3, wherein each of the first and second sourcedrain regions extend to a depth below or equal to the top side of the ridge.
10. The integrated circuit according to claim 4, wherein each of the first and second sourcedrain regions extend to a depth below or equal to the top side of the ridge.
11. The integrated circuit according to claim 1, further comprising:
bit lines extending along a second direction intersecting the first direction, each of the second sourcedrain regions being connected with one bit line, wherein the bit lines are formed on the substrate surface to be in contact with a plurality of second sourcedrain regions.
12. The integrated circuit according to claim 1, wherein an isolating spacer is disposed between each first sourcedrain region and corresponding gate electrode and between each second sourcedrain region and corresponding gate electrode, the isolating spacer having a larger thickness than the gate isolating layer for each gate electrode.
13. The integrated circuit according to claim 12, wherein each isolating spacer is made of silicon dioxide.
14. The integrated circuit according to claim 1, wherein each of the active areas of one row of active areas are isolated from each other by isolation trenches filled with an isolating material.
15. The integrated circuit according to claim 6, wherein the storage capacitor comprises a storage electrode and a counter electrode, and the storage and counter electrodes are disposed above the substrate surface.
16. The integrated circuit according to claim 11, wherein the bitlines are in direct contact with the second sourcedrain regions such that no bitline contact is disposed between the bitlines and the second sourcedrain regions.
17. The integrated circuit according to claim 11, further comprising a storage capacitor is disposed above the bitlines.
18. An integrated circuit including a memory cell array, the memory cell array comprising:
a plurality of memory cells, each of the memory cells including a transistor with a first sourcedrain region and a second sourcedrain region, wherein the first and second sourcedrain regions are distanced from and oriented with respect to each other along a first direction; and
a plurality of word lines, wherein each of the word lines includes a length that extends in the first direction, and wherein each transistor comprises a gate electrode configured to connect with two adjacent word lines.
19. The integrated circuit according to claim 18, further comprising:
active areas arranged in rows, wherein the transistors are formed in the active areas; and
a plurality of isolation grooves, each isolation groove comprising two word lines;
wherein adjacent rows of active areas are separated from each other by the isolation grooves.
20. The integrated circuit according to claim 18, further comprising bitlines extending along a second direction intersecting the first direction.
21. The integrated circuit according to claim 20, wherein the bitlines are in contact with a substrate surface such that no bitline contact is disposed between the bitlines and a sourcedrain region of a corresponding transistor.
22. The integrated circuit according to claim 21, wherein a storage capacitor is disposed above the bitlines.
23. The integrated circuit according to claim 18, further comprising:
a plurality of bitlines; and
a plurality of storage capacitors disposed above the bitlines.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A boot file generation method comprising:
creating a boot template file comprising symbolic variable names that point to configuration registers within a programmable device;
receiving user module selections with delineation of preferred configurations and functions associated with components of said programmable device;
generating application files automatically based upon user selected configurations and functions; and
substituting said symbolic variable names with actual configuration register names.
2. A boot file generation method of claim 1 further comprising automatic interrupt vector mapping which assigns the appropriate providing interrupt processing routine vector.
3. A boot file generation method of claim 1 further comprising:
providing an interface for selecting applicable user modules;
facilitating programming of desired functionality into the programmable device; and
executing an assembler process.
4. A boot file generation method of claim 3 wherein said user module is a preconfigured function that may be based on more than one lock that work as a peripheral on the programmable device.
5. A boot file generation method of claim 3 further comprising:
viewing and modifying user module parameters including setting global parameters;
specifying interconnections between the selected user modules; and
delineating a pin-out for each functional block making a connection between the software configuration and the hardware of the programmable device.
6. A boot file generation method of claim 1 further comprising emulating the programmable device using an in-circuit emulator for debugging.
7. A boot file generation method of claim 6 wherein the emulator allows the programmable device to be tested in a hardware environment while device activity is viewed and debugged in a software environment.
8. A boot file generation method of claim 3 further comprising:
updating existing assembly source and C compiler code for device configurations; and
generating application program interfaces (APIs) and interrupt service routines (ISRs).
9. A boot file generation method of claim 3 wherein the assembler process comprises operating on an assembly-language source code to produce executable code.
10. A boot file generation method of claim 9 further comprising compiling and building code into an executable file.
11. A boot file generation method of claim 9 further comprising linking programmed functionalities including device configuration.
12. A circuit comprising:
a bus for communicating data;
a microprocessor for processing data, said microprocessor coupled to said bus;
a functional component coupled to said bus, wherein said functional component includes a plurality of functional blocks programmable to provide a plurality of functions and configurations; and
a memory for storing configuration information including information associated with a boot file, wherein said boot file is created utilizing a template comprising symbolic register names that are substituted by the actual register name, said memory coupled to said bus.
13. The circuit of claim 12, wherein a component of said circuit is programmable according to a configuration information stored in said memory.
14. A boot file creation method comprising:
assigning variable symbolic register names to a user module;
establishing an association between the variable symbolic register names and actual configuration register names; and
replacing the variable symbolic register names with actual configuration register names.
15. The boot file creation method of claim 14 further comprising loading the boot file on a target device.
16. A boot file creation method of claim 14 further comprising utilizing a boot template to establish the association between the variable symbolic registers names and actual configuration register names.
17. A boot file creation method of claim 16 further utilizing the boot template to replace the variable symbolic register names with the actual configuration register names.
18. A boot file creation method of claim 14 further comprising regenerating the boot file is when a device configuration changes.
19. A boot file creation method of claim 14 wherein the boot file is created and loaded on a target device by a design tool.