1. A method comprising:
receiving, at a storage controller, data to be stored in solid state memory comprising multiple solid state physical memory devices;
dividing, by the storage controller, the received data into logical data blocks corresponding to the solid state memory;
assigning, by the storage controller, the logical data blocks to a logical block grouping comprising at least one physical data storage block from two or more of the multiple solid state physical memory devices;
storing the logical data blocks in physical data storage blocks, of the logical block grouping, designated for storage of persisted data within the logical block grouping;
determining, by the storage controller, a code that corresponds to the persisted data stored in the logical block grouping; and
storing, by the storage controller, the code in at least one physical data storage block designated for storage of the code that corresponds to the persisted data stored in the logical block grouping.
2. The method of claim 1, wherein the multiple solid state physical memory devices are FLASH memory devices.
3. The method of claim 1, wherein the determining is a logical XOR operation.
4. The method of claim 1, wherein the multiple solid state physical memory devices and the storage controller comprise a single memory storage device, and the logical block grouping corresponds to a logical block grouping used by the storage controller to carry out memory management in the single memory storage device.
5. The method of claim 1, wherein each of the multiple solid state physical memory devices comprises a single integrated circuit die comprising at least one physical data storage block, wherein a physical data storage block comprises a block of solid state memory formed on the integrated circuit die and is individually addressable along with other blocks of solid state memory formed on the same integrated circuit die.
6. The method of claim 1 further comprising:
recovering, by the storage controller, the persisted data stored in a selected physical data storage block by identifying the logical block grouping to which the logical data block corresponding to the selected physical data storage block is assigned, reading the persisted data and the code stored in the identified logical block grouping, and comparing the code to the read persisted data other than the persisted data stored in the selected physical data storage block.
7. The method of claim 6, wherein the comparing is a logical XOR operation.
8. The method of claim 1, wherein determining the code comprises:
storing, in a buffer memory, a first logical data block of the logical block grouping as a buffered value;
for each of the remaining logical data blocks in the logical block grouping,
comparing, by the storage controller, the remaining logical data block to the buffered value to determine a comparison value, and
storing the comparison value as the buffered value in the buffer memory; and
determining, by the storage controller, a value that, when compared to the buffered value, results in a predetermined value.
9. The method of claim 9, wherein the buffer memory comprises multiple buffer memories, and at least one of the buffer memories comprises a single port memory.
10. An electronic device for storing data, comprising:
an input port configured to receive data;
a comparison buffer memory to hold a comparison value;
a comparison circuit to compare each of multiple logical blocks, into which the data is divided, to the comparison value to determine a new comparison value to hold in the comparison buffer memory; and
a solid state data storage memory to store the logical blocks and a recovery code corresponding to the comparison value, wherein data from at least one of the stored logical blocks is recoverable by combining data from one or more unselected ones of the stored logical blocks and the recovery code.
11. The device of claim 10, wherein the solid state data storage memory is a FLASH memory.
12. The device of claim 10, wherein the comparison circuit performs a logical XOR operation.
13. The device of claim 10, wherein the buffer memory comprises multiple buffer memories, and at least one of the buffer memories comprises a single port memory.
14. The device of claim 10, wherein the recovery code is determined by determining a value that, when compared to the comparison value, results in a predetermined value.
15. The device of claim 10, comprising a processor programmed by software to effect the comparison circuit.
16. The device of claim 15, wherein the comparison circuit performs a logical XOR operation.
17. The device of claim 10, wherein the solid state data storage memory comprises multiple solid state physical memory devices.
18. The device of claim 17, wherein each of the multiple solid state physical memory devices comprises a single integrated circuit die comprising at least one physical data storage block, wherein a physical data storage block comprises a block of solid state memory formed on the integrated circuit die and is individually addressable along with other blocks of solid state memory formed on the same integrated circuit die.
19. The device of claim 17, wherein the device interfaces with a host device as a single data storage device.
20. A method comprising:
receiving a request for data stored in solid state memory comprising multiple solid state physical memory devices;
identifying, by a storage controller, a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more of the multiple solid state physical memory devices;
reading stored data and a code stored in the identified logical block grouping; and
comparing the code to the stored data to assess the requested data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer implemented method for optimizing memory page sizes during runtime, the computer implemented method comprising:
identifying a process from a policy file, the policy file containing at least one policy based threshold for a set of stated desired policies;
monitoring the process during runtime;
determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds:
responsive to determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, executing a performance projection for the process, wherein the computer implemented step of executing the performance projection for the process further comprises: examining a plurality of logical addresses for a plurality of referenced pages from a plurality of translation lookaside buffer misses; identifying pages of the plurality of referenced pages that are logically located adjacent to one another for consideration as a larger page size; and determining a number of translation lookaside buffer misses that would have occurred using the larger page size;
determining from the performance projection whether the process would experience a performance benefit from a different page size; and
responsive to determining that the process would experience the performance benefit from the different page size, changing a page size for the process.
2. The computer implemented method of claim 1, wherein the computer implemented step of monitoring the process during runtime further comprises:
gathering system statistics by a resource usage profile, wherein the system statistics are selected from a group consisting of central processing unit resource usage, memory access patterns, page translation misses from a translation lookaside buffer, cache misses from data and instruction caches, and combinations thereof.
3. The computer implemented method of claim 2, wherein the computer implemented step of determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, comprises:
determining whether the cache misses from data and instruction caches exceeds a cache miss threshold of the at least one policy based threshold.
4. The computer implemented method of claim 1, wherein the computer implemented step of determining from the performance projection whether the process would experience the performance benefit from the different page size further comprises:
determining whether the number of translation lookaside buffer misses that would have occurred using the larger page size is less than the plurality of translation lookaside buffer misses for an original page size.
5. The computer implemented method of claim 1, wherein the computer implemented step of changing the page size for the process further comprises:
making a kernel call to a system kernel; and
performing page promotion or demotion for the process within the system kernel.
6. The computer implemented method of claim 1, wherein the computer implemented step of determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, further comprises:
determining whether the process exceeds a processor usage policy based threshold; and
determining whether the process exceeds a memory usage policy based threshold.
7. A non-transitory computer readable storage medium having computer usable instructions encoded thereon for optimizing memory page sizes during runtime, the computer readable storage medium comprising:
first instructions for identifying a process from a policy file, the policy file containing at least one policy based threshold for a set of stated desired policies;
second instructions for monitoring the process during runtime;
third instructions for determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds;
fourth instructions, responsive to determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, for executing a performance projection for the process, wherein the fourth instructions for executing the performance projection for the process further comprises: instructions for examining a plurality of logical addresses for a plurality of referenced pages from a plurality of translation lookaside buffer misses; instructions for identifying pages of the plurality of referenced pages that are logically located adjacent to one another for consideration as a larger page size; and instructions for determining a number of translation lookaside buffer misses that would have occurred using the larger page size;
fifth instructions for determining from the performance projection whether the process would experience a performance benefit from a different page size; and
sixth instructions, responsive to determining that the process would experience the performance benefit from the different page size, for changing a page size for the process.
8. The non-transitory computer readable storage medium of claim 7, wherein the second instructions for monitoring the process during runtime further comprises:
instructions for gathering system statistics by a resource usage profile, wherein the system statistics are selected from a group consisting of central processing unit resource usage, memory access patterns, page translation misses from a translation lookaside buffer, cache misses from data and instruction caches, and combinations thereof.
9. The non-transitory computer readable storage medium of claim 8, wherein the third instructions for determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, comprises:
determining whether the cache misses from data and instruction caches exceeds a cache miss threshold of the at least one policy based threshold.
10. The non-transitory computer readable storage medium of claim 7, wherein the fifth instructions for determining from the performance projection whether the process would experience the performance benefit from the different page size further comprises:
instructions for determining whether the number of translation lookaside buffer misses that would have occurred using the larger page size is less than the plurality of translation lookaside buffer misses for an original page size.
11. The non-transitory computer readable storage medium of claim 7, wherein the sixth instructions for changing the page size for the process further comprises:
instructions for making a kernel call to a system kernel; and
instructions for performing page promotion or demotion for the process within the system kernel.
12. The non-transitory computer readable storage medium of claim 7, wherein the fourth instructions for determining whether the process exceeds the set of stated desired policies from the set of policy based thresholds, further comprises:
instructions for determining whether the process exceeds a processor usage policy based threshold; and
determining whether the process exceeds a memory usage policy based threshold.
13. A data processing system comprising:
a storage having computer usable instructions encoded thereon for optimizing memory page sizes during runtime;
a bus system connecting the storage to a processor; and
a processor, wherein the processor executes the computer usable instructions:
to identify a process from a policy file, the policy file containing at least one policy based threshold for a set of stated desired policies;
to monitor the process during runtime; to determine whether the process exceeds the set of stated desired policies from the at least one policy based threshold;
responsive to determining whether the process exceeds the set of stated desired policies from the at least one policy based threshold, to execute a performance projection for the process, wherein executing the performance projection for the process further comprises the processor executing the computer usable instructions: to examine a plurality of logical addresses for a plurality of referenced pages from a plurality of translation lookaside buffer misses; to identify pages of the plurality of referenced pages that are logically located adjacent to one another for consideration as a larger page size; and to determine a number of translation lookaside buffer misses that would have occurred using the larger page size;
to determine from the performance projection whether the process would experience a performance benefit from a different page size; and
responsive to determining that the process would experience the performance benefit from the different page size, to change a page size for the process.
14. The data processing system of claim 13, wherein the processor executing the computer usable instructions to monitor the process during runtime further comprises the processor executing the computer usable instructions:
to gather system statistics by a resource usage profile, wherein the system statistics are selected from a group consisting of central processing unit resource usage, memory access patterns, page translation misses from a translation lookaside buffer, cache misses from data and instruction caches, and combinations thereof.
15. The data processing system of claim 14, wherein the processor executing the computer usable instructions to determine whether the process exceeds the set of stated desired policies from the at least one policy based threshold, comprises the processor executing the computer usable instructions:
to determine whether the cache misses from data and instruction caches exceeds a cache miss threshold of the at least one policy based threshold.
16. The data processing system of claim 13, wherein the processor executing the computer usable instructions to determine from the performance projection whether the process would experience the performance benefit from the different page size further comprises the processor executing the computer usable instructions:
to determine whether the number of translation lookaside buffer misses that would have occurred using the larger page size is less than the plurality of translation lookaside buffer misses for an original page size.
17. The data processing system of claim 13, wherein the processor executing the computer usable instructions to change the page size for the process further comprises the processor executing the computer usable instructions:
to make a kernel call to a system kernel; and
to perform page promotion or demotion for the process within the system kernel.
18. The data processing system of claim 13, wherein the processor executing the computer usable instructions to determine whether the process exceeds the set of stated desired policies from the at least one policy based threshold, further comprises the processor executing the computer usable instructions:
to determine whether the process exceeds a processor usage policy based threshold; and
to determine whether the process exceeds a memory usage policy based threshold.