1. An integrated circuit disposed on a semiconductor die, wherein the integrated circuit comprises a plurality of columns extending from a first column on a first side of the semiconductor die to a second column on a second side of the semiconductor die opposite the first side, each of the columns is substantially completely occupied by a plurality of tiles, wherein substantially all of the tiles of each of the columns have an identical width, wherein a width of one of the columns differs from a width of another of the columns, and wherein there are inputoutput interconnect tiles in a third column enabling connections between columns, and inputoutput block tiles disposed in at least two of the columns, the inputoutput block tiles enabling internal connections to circuits in an adjacent column by way of the third column of inputoutput interconnect tiles and enabling external connections to first associated bond bumps of the semiconductor die, and the inputoutput block tiles in at least one of the columns of inputoutput block tiles being in a column other than the first column or the second column and an inputoutput block tile of the at least one column being disposed in a central location to receive a clock signal by way of a bond bump of the inputoutput block tile, wherein the first column on the first side of the semiconductor die comprises a plurality of multi-gigabit transceivers enabling external connections to second associated bond bumps of the semiconductor die, the plurality of multi-gigabit transceivers being coupled to a fourth column of inputoutput interconnect tiles.
2. The integrated circuit of claim 1, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein each column of the plurality of columns extends from the third side to the fourth side.
3. The integrated circuit of claim 1, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein one of the columns is a column of configurable logic block tiles, the column of configurable logic block tiles extending from the third side to the fourth side such that a first configurable logic block tile is disposed adjacent the third side and such that a second configurable logic block tile is disposed adjacent the fourth side.
4. The integrated circuit of claim 3, wherein all the configurable logic block tiles of the column of configurable logic block tiles are identical tiles.
5. The integrated circuit of claim 3, wherein there is no inputoutput block tile disposed between the column of configurable logic block tiles and the third side of the semiconductor die, and wherein there is no inputoutput block tile disposed between the column of configurable logic block tiles and the fourth side of the semiconductor die.
6. The integrated circuit of claim 1, wherein each of the inputoutput block tiles is coupled by a conductor to an associated bond bump, and wherein circuitry of the inputoutput block tile can be configured to use the bond bump to receive a signal onto the integrated circuit via the inputoutput block tile.
7. The integrated circuit of claim 1, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein the at least one column of inputoutput block tiles extends from the third side to the fourth side such that an inputoutput block tile is disposed adjacent the third side and such that a second inputoutput block tile is disposed adjacent the fourth side.
8. The integrated circuit of claim 7, wherein all the inputoutput block tiles of the column of inputoutput block tiles are identical tiles.
9. The integrated circuit of claim 1, wherein one of the columns includes at least four different types of tiles.
10. The integrated circuit of claim 1, wherein a column of the plurality of columns includes a plurality of clock distribution tiles.
11. The integrated circuit of claim 1, wherein over ninety-five percent of the die area of each of the columns is occupied by a single type of tile.
12. The integrated circuit of claim 11, wherein in addition to the single type of tile each of the columns also includes a plurality of clock distribution tiles.
13. The integrated circuit of claim 1, wherein substantially all the inputoutput block tiles are laid out to have either a first orientation or a second orientation, where the second orientation is a mirror image of the first orientation.
14. An integrated circuit disposed on a semiconductor die, wherein the integrated circuit comprises a plurality of columns extending from a first column on a first side of the semiconductor die to a second column on a second side of the semiconductor die opposite the first side, each of the columns is substantially completely occupied by a plurality of tiles, wherein substantially all of the tiles of each of the columns have an identical width, wherein a width of one of the columns differs from a width of another of the columns, and wherein there are inputoutput interconnect tiles in a third column enabling connections between columns, and inputoutput block tiles disposed in at least three of the columns, the inputoutput block tiles enabling internal connections to circuits in an adjacent column by way of the third column of inputoutput interconnect tiles and enabling external connections to first associated bond bumps of the semiconductor die, and the inputoutput block tiles in at least one of the columns of inputoutput block tiles being in a column other than the first column or the second column and an inputoutput block tile of the at least one column being disposed in a central location to receive a clock signal by way of a bond bump of the inputoutput block tile, wherein the first column on the first side of the semiconductor die comprises a plurality of multi-gigabit transceivers enabling external connections to second associated bond bumps of the semiconductor die, the plurality of multi-gigabit transceivers being coupled to a fourth column of inputoutput interconnect tiles.
15. The integrated circuit of claim 14, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein each column of the plurality of columns extends from the third side to the fourth side.
16. The integrated circuit of claim 14, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein one of the columns is a column of configurable logic block tiles, the column of configurable logic block tiles extending from the third side to the fourth side such that a first configurable logic block tile is disposed adjacent the third side and such that a second configurable logic block tile is disposed adjacent the fourth side.
17. The integrated circuit of claim 14, wherein each of the inputoutput block tiles is coupled by a conductor to an associated bond bump, and wherein circuitry of the inputoutput block tile can be configured to use the bond bump to receive a signal onto the integrated circuit via the inputoutput block tile.
18. The integrated circuit of claim 14, wherein the semiconductor die has the first side, the second side parallel to the first side, a third side, and a fourth side parallel to the third side, and wherein at least one of the columns is a column of inputoutput block tiles, the column of inputoutput block tiles extending from the third side to the fourth side such that an inputoutput block tile is disposed adjacent the third side and such that a second inputoutput block tile is disposed adjacent the fourth side.
19. The integrated circuit of claim 18, wherein all the inputoutput block tiles of the column of inputoutput block tiles are identical tiles.
20. The integrated circuit of claim 14, wherein substantially all the inputoutput block tiles are laid out to have either a first orientation or a second orientation, where the second orientation is a mirror image of the first orientation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Fluid product dispenser comprising:
a variable volume reservoir (12) that varies by displacement of a mobile wall (11) in order to reduce the volume of the reservoir,
a distribution orifice (32), and
actuation means (2) to move the mobile wall (11) of the reservoir, wherein the actuation means rotate and comprise a thread (21) engaged with the reservoir.
2. Dispenser according to claim 1, in which the reservoir (12) comprises at least one displacement flange (13) fixed to the mobile wall (11) and is engaged by threading (21).
3. Dispenser according to claim 1, comprising a body (3), the rotating actuation means (2) being fixed free to rotate in the said body (3) without any translation movement with respect to the said body.
4. Dispenser according to claim 3, in which the body (3) forms a part (31) of the reservoir (12).
5. Dispenser according to claim 4, in which the reservoir (12) comprises a bellows (1) with a sealed connection with the body (3), the said bellows (1) forming the mobile wall (11).
6. Dispenser according to claim 5, in which the bellows (1) comprises a sealed attachment collar (15) engaged with a connection sleeve (35) formed by the body (3).
7. Dispenser according to claim 3, in which the distribution orifice (31) is formed in the body (3).
8. Dispenser according to claim 6, in which the mobile wall (11) is connected to the attachment collar (15) through a deformable wall (14).
9. Dispenser according to claim 1, in which the actuation means (2) form a bottom (22) for the dispenser.
10. Dispenser according to claim 1, in which the actuation means (2) comprise a peripheral gripping device (23) capable of driving the actuation means in free rotation in the body.