What is claimed is:
1. A method of operating a computer system for targeting one or more digital assets on a distribution server connected to one or more networks so that the digital assets are compatible with one or more target nodes connected to the networks, the method comprising:
examining the one or more digital assets to determine an asset type of the digital asset;
if the asset type is Relational Data (RD), retrieving one or more where clauses of the digital asset;
executing a token replacement operation on the where clause to create a transformed where clause;
running a query on one or more tables specified in the digital asset using the transformed where clause, the query returning one or more returned records, the returned records correlating with the target node; and
storing the returned record in the digital asset.
2. The method of claim 1, wherein the target node is registered with the computer system.
3. The method of claim 1, wherein the target node is one of a class of target nodes registered with the computer system.
4. The method of claim 1, wherein the digital asset is in a neutral or normalized format.
5. The method of claim 1, wherein the where clause is stored in an extended environment section of the digital asset.
6. The method of claim 1, wherein the asset type is any one of the set of entity bean (EB), reference data (RD) and entity data (ED).
7. The method of claim 1, wherein the token replacement operation comprises a string replacement operation that retrieves a replacement value from a node specification corresponding to the targeted node.
8. The method of claim 1, wherein an SQL query using the transformed where clause query returns data that is placed in a logicdata (LD) section of the digital asset.
9. The method of claim 1, wherein the asset type is Relational Data (RD) and the where clause has tokens that need to be replaced using information in a node’s registry of the target node.
10. The method of claim 1, wherein the asset type is Reference Data (RD) and the where clause has tokens that need to be replaced using information in a node’s registry of the target node.
11. The method of claim 1, wherein an SQL query using the transformed where clause query returns data that is placed in a logicdata (LD) section of the asset.
12. The method of claim 1, wherein the asset type is Entity Bean (EB) and a query has to be performed for each target node in a set of target nodes.
13. The method of claim 1, wherein the asset type is Entity Data (ED) and a query has to be performed for each target node in a set of target nodes.
14. The method of claim 13, wherein the query queries data directly correlating to an individual end user.
15. The method of claim 13, wherein the query comprises the tokens, and wherein the target node provides filtering for the capture of client activity logging.
16. The method of claim 15, wherein the client activity logging data is recorded in the ED in order to synchronize such data back into the source environment.
17. The method of claim 13, wherein the query queries the status of the current orders for an individual customer.
18. A method for targeting a digital asset to a multi-tiered network node, comprising:
selecting a target asset adapter associated with the digital asset;
determining an asset type associated with the digital asset;
retrieving a descriptor from a first data structure associated with the digital asset;
transforming the descriptor using a token replacement operation having a token associated with the node;
running a query, using the transformed descriptor, on a table specified in the first data structure associated with the digital asset;
creating a second data structure using data returned by the query; and
inserting the second data structure into the first data structure associated with the digital asset.
19. The method of claim 18, wherein the digital asset is a Reference Data (RD) type.
20. The method of claim 18, wherein the digital asset is an Entity Data (ED) type.
21. The method of claim 18, wherein the first data structure comprises a LogicData (LD) part and an Extended Environment (EE) part.
22. The method of claim 21, wherein the descriptor is retrieved from the EE part.
23. The method of claim 21, wherein the second data structure is inserted into the LD part.
24. The method of claim 18, wherein the token replacement operation is a basic string replacement operation.
25. The method of claim 18, wherein the token is retrieved from a specification associated with the node.
26. The method of claim 18, wherein the token is retrieved from a registry associated with the node.
27. The method of claim 18, wherein the query is a SQL query and the data returned by the query are records.
28. The method of claim 18, wherein the table resides in a source tier, and the query is run in the source tier.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for synchronizing clock signals, the system comprising:
a clock unit, wherein the clock unit is coupled to receive a reference clock signal and to output a plurality of domain clock signals, wherein each of the domain clock signals has a different frequency with respect to the other domain clock signals, the clock unit including a plurality of domain clock units each configured to provide a corresponding one of the domain clock signals;
a synchronization unit, wherein the synchronization unit is configured to receive the reference clock signal, wherein the synchronization unit is configured to assert and provide, to each of the plurality of domain clock units of the clock unit, a synchronization pulse at a rate equivalent to a beat frequency of the plurality of domain clock signals, the beat frequency being a frequency in which a given cyclic pattern of the plurality of domain clock signals repeats itself with respect to the reference clock signal, and wherein the clock unit is configured to align with each other clock signal edges of the plurality of domain clock signals and the reference clock signal responsive to receiving the synchronization pulse.
2. The system as recited in claim 1, wherein each of the plurality of domain clock units is a phase locked loop (PLL), and wherein each of the PLLs is coupled to receive the reference clock signal.
3. The system as recited in claim 2, wherein each of the plurality of PLLs is configured to receive the synchronization pulse.
4. The system as recited in claim 3, wherein each of the plurality of PLLs includes a counter, and wherein the counter is reset responsive to asserting the synchronization pulse.
5. The system as recited in claim 2, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency greater than that of the reference clock signal.
6. The system as recited in claim 2, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency less than that of the reference clock signal.
7. The system as recited in claim 1, wherein the synchronization unit includes a counter, wherein the counter is configured to receive the reference clock signal.
8. The system as recited in claim 7, wherein the counter is configured to sequentially produce N different states, and wherein the beat frequency is a frequency of the reference clock signal divided by N.
9. The system as recited in claim 1, wherein each of the plurality of domain clock units is a delay locked loop (DLL), and wherein each of the DLLs is coupled to receive the reference clock signal.
10. The system as recited in claim 9, wherein each of the plurality of DLLs is configured to receive the synchronization pulse.
11. The system as recited in claim 10, wherein each of plurality of the DLLs includes a counter, and wherein an assertion of the synchronization pulse causes the counter to reset.
12. The system as recited in claim 9, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is greater than the frequency of the reference clock signal.
13. The system as recited in claim 9, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is less than the frequency of the reference clock signal.
14. The system as recited in claim 1, wherein the clock signal edges are rising edges.
15. The system as recited in claim 1, wherein the clock signal edges are falling edges.
16. A method for synchronizing clock signals, the method comprising:
receiving a reference clock signal, wherein the reference clock signal is received by a clock unit and a synchronization unit, wherein the clock unit is configured to output a plurality of domain clock signals, and wherein each of the domain clock signals has a different frequency with respect to the other domain clock signals, wherein the clock unit includes a plurality of domain clock units each configured to provide a corresponding one of the domain clock signals;
asserting a synchronization pulse, wherein the synchronization pulse is asserted by the synchronization unit, and wherein the synchronization pulse is asserted at a rate equivalent to a beat frequency of the plurality of the domain clock signals, the beat frequency being a frequency in which a given cyclic pattern of the plurality of domain clock signals repeats itself with respect to the reference clock signal;
the plurality of domain clock units of the clock unit receiving the synchronization pulse; and
aligning, with each other, clock signal edges of the plurality of domain clock signals and the reference clock signal responsive to said receiving the synchronization pulse.
17. The method as recited in claim 16, wherein each of the plurality of domain clock units is a phase locked loop (PLL), and wherein each of the PLLs is coupled to receive the reference clock signal.
18. The method as recited in claim 17, wherein each of the plurality of PLLs is configured to receive the synchronization pulse.
19. The method as recited in claim 18, wherein each of the plurality of PLLs includes a counter, and wherein the counter is reset responsive to said asserting the synchronization pulse.
20. The method as recited in claim 17, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency greater than that of the reference clock signal.
21. The method as recited in claim 17, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency less than that of the reference clock signal.
22. The method as recited in claim 16, wherein the synchronization unit includes a counter, wherein the counter is configured to receive the reference clock signal.
23. The method as recited in claim 22, wherein the counter is configured to sequentially produce N different states, and wherein the beat frequency is a frequency of the reference clock signal divided by N.
24. The method as recited in claim 16, wherein each of the plurality of domain clock units is a delay locked loop (DLL), and wherein each of the plurality of DLLs is coupled to receive the reference clock signal.
25. The method as recited in claim 24, wherein each of the plurality of DLLs is configured to receive the synchronization pulse.
26. The method as recited in claim 25, wherein each of the plurality of DLLs includes a counter, and wherein an assertion of the synchronization pulse caused the counter to reset.
27. The method as recited in claim 24, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is greater than that of the reference clock signal.
28. The method as recited in claim 24, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is less than that of the reference clock signal.
29. The method as recited in claim 16, wherein the clock signal edges are rising edges.
30. The method as recited in claim 16, wherein the clock signal edges are falling edges.
31. An IO node comprising:
a first transceiver unit and a second transceiver unit comprising a first clock domain and a second clock domain, respectively;
an IO tunnel, the IO tunnel comprising a third clock domain;
a plurality of clock domain synchronizers, including first and second clock domain synchronizers coupling the IO tunnel to the first transceiver unit and the second transceiver unit, respectively, wherein each of the plurality of clock domain synchronizers includes:
a clock unit, wherein the clock unit is coupled to receive a reference clock signal and to output a plurality of domain clock signals, wherein each of the domain clock signals has a different frequency with respect to the other domain clock signals, the clock unit including a plurality of domain clock units each configured to provide a corresponding one of the domain clock signals;
a synchronization unit, wherein the synchronization unit is configured to receive the reference clock signal, wherein the synchronization unit is configured to assert and provide, to each of the plurality of domain clock units of the clock unit, a synchronization pulse at a rate equivalent to a beat frequency of the plurality of domain clock signals, the beat frequency being a frequency in which a given cyclic pattern of the plurality of domain clock signals repeats itself with respect to the reference clock signal, and wherein the clock unit is configured to align with each other clock signal edges the plurality of the domain clock signals and the reference clock signal responsive to receiving the synchronization pulse.
32. The IO node as recited in claim 31, wherein each of the plurality of domain clock units is a phase locked loop, and wherein each of the PLLs is coupled to receive the reference clock signal.
33. The IO node as recited in claim 32, wherein each of the plurality of PLLs is configured to receive the synchronization pulse.
34. The IO node as recited in claim 33, wherein each of the plurality of PLLs includes a counter, and wherein the counter is reset responsive to asserting the synchronization pulse.
35. The IO node as recited in claim 32, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency greater than that of the reference clock signal.
36. The IO node as recited in claim 32, wherein at least one of the plurality of PLLs is configured to output a domain clock signal having a frequency less than that of the reference clock signal.
37. The IO node as recited in claim 31, wherein the synchronization unit includes a counter, wherein the counter is configured to receive the reference clock signal.
38. The IO node as recited in claim 37, wherein the counter is configured to sequentially produce N different states, and wherein the beat frequency is a frequency of the reference clock signal divided by N.
39. The IO node as recited in claim 31, wherein each of the plurality of domain clock units is a delay locked loop (DLL), and wherein each of the DLLs is coupled to receive the reference clock signal.
40. The IO node as recited in claim 39, wherein each of the plurality of DLLs is configured to receive the synchronization pulse.
41. The IO node as recited in claim 40, wherein each of plurality of the DLLs includes a counter, and wherein an assertion of the synchronization pulse causes the counter to reset.
42. The IO node as recited in claim 39, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is greater than the frequency of the reference clock signal.
43. The IO node as recited in claim 39, wherein at least one of the plurality of DLLs is configured to output a domain clock signal having a frequency that is less than the frequency of the reference clock signal.
44. The IO node as recited in claim 31, wherein the clock signal edges are rising edges.
45. The IO node as recited in claim 31, wherein the clock signal edges are falling edges.
46. The IO node as recited in claim 31, wherein the first transceiver unit is configured to be coupled to a first packet bus link, and wherein the second transceiver unit is configured to be coupled to a second packet bus link.
47. The IO node as recited in claim 31, wherein the IO node includes a peripheral bus interface configured to be coupled to a peripheral bus, wherein the peripheral bus interface comprises a fourth clock domain.
48. The IO node as recited in claim 47, wherein the plurality of clock domain synchronizers includes a third clock domain synchronizer, wherein the peripheral bus interface is coupled to the IO tunnel by the third clock domain synchronizer.