1. A receiving device for wireless communication, the receiving device comprising: processing circuitry configured to: receive maximum dimension information indicating a maximum number of rows of a channel state information feedback matrix, the maximum dimension information being included in a transmit beamforming capability field of a HT (high throughput) capabilities element defined in wireless network standard IEEE 802.11; and receive signals from a transmitting device based at least in part on information included in the HT capabilities element, so as to establish a wireless communication channel between the transmitting device and the receiving device;
wherein the maximum dimension information is represented by two bits, the two bits being located adjacent to a bit field including an information of maximum beamformer capability.
2. The receiving device of claim 1, wherein the HT capabilities element is present in a management frame.
3. The receiving device of claim 2, wherein the management frame includes:
a beacon signal, a measure pilot, an association response, a re-association response, andor a probe response.
4. The receiving device of claim 1, wherein the transmit beamforming capability field further includes both implicit beamforming capability information and explicit beamforming capability information.
5. The receiving device of claim 1, further comprising:
a plurality of antennas configured to transmit or receive signals including channel estimation capability information.
6. The receiving device of claim 5, wherein a number of the plurality of antennas is two.
7. The receiving device of claim 5, wherein a number of the plurality of antennas is three.
8. The receiving device of claim 5, further comprising:
a plurality of digital filters configured to perform band limitation, the number of the plurality of digital filters being equal to a number of the plurality of antennas.
9. A mobile receiving apparatus for wireless communication, the mobile receiving apparatus comprising: a plurality of antennas; and processing circuitry configured to: receive maximum dimension information indicating a maximum number of rows of a channel state information feedback matrix, the maximum dimension information being included in a transmit beamforming capability field of a HT (high throughput) capabilities element defined in wireless network standard IEEE 802.11; and receive signals from a transmitting device based at least in part on information included in the HT capabilities element, so as to establish a wireless communication channel between the transmitting device and the mobile receiving apparatus;
wherein the maximum dimension information is represented by two bits, the two bits being located adjacent to a bit field including an information of maximum beamformer capability.
10. The mobile receiving apparatus of claim 9, wherein the mobile receiving apparatus is a mobile telephone.
11. A receiving method for wireless communication, the receiving method comprising: receiving maximum dimension information indicating a maximum number of rows of a channel state information feedback matrix, the maximum dimension information being included in a transmit beamforming capability field of a HT (high throughput) capabilities element defined in wireless network standard IEEE 802.11; and receiving signals from a transmitting device based at least in part on information included in the HT capabilities element, so as to establish a wireless communication channel between the transmitting device and the receiving device;
wherein the maximum dimension information is represented by two bits, the two bits being located adjacent to a bit field including an information of maximum beamformer capability.
12. The receiving method of claim 11, wherein the HT capabilities element is present in a management frame.
13. The receiving method of claim 12, wherein the management frame includes:
a beacon signal, a measure pilot, an association response, a re-association response, andor a probe response.
14. The receiving device of claim 11, wherein the transmit beamforming capability field further includes both implicit beamforming capability information and explicit beamforming capability information.
15. The mobile receiving apparatus of claim 9, wherein a number of the plurality of antennas is two.
16. The mobile receiving apparatus of claim 9, wherein a number of the plurality of antennas is three.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit packaging method comprising:
fabricating a package module from successive build-up layers which define circuit interconnections;
forming a cavity on a top-side of the package module;
attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact;
disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module; and
coupling the metallic layer that is attached to the chip onto the top-side of the package module.
2. The integrated circuit packaging method recited in claim 1 wherein attaching the metalized back-side of the chip onto the metallic layer is done with a high temperature process.
3. The integrated circuit packaging method recited in claim 1 wherein attaching the metalized back-side of the chip onto the metallic layer is done with a diffusion soldering process.
4. The integrated circuit packaging method recited in claim 1 wherein the metallic layer is a metal foil layer.
5. The integrated circuit packaging method recited in claim 1 wherein the back-side of the chip has a low ohmic contact.
6. The integrated circuit packaging method recited in claim 5 wherein current flows vertically between the low ohmic contact and the at least one forward contact of the chip.
7. The integrated circuit packaging method recited in claim 6 wherein the low ohmic contact is electrically connected to the metallic layer, and therethrough to one or more vias formed in the package module.
8. The integrated circuit packaging method recited in claim 1 wherein the metallic layer has thermally conductive properties.
9. The integrated circuit packaging method recited in claim 8 further comprising attaching the metallic layer to a heat sink.
10. The integrated circuit packaging method recited in claim 1 wherein the chip further comprises through silicon vias.
11. The integrated circuit packaging method recited in claim 1 wherein the metallic layer is coupled to the back-side of the chip or the top-side of the package module by way of an isolating middle layer.
12. An integrated circuit package comprising:
a package module formed from successive build-up layers which define circuit interconnections;
a cavity formed on a top-side of the package module;
a chip having a front-side with at least one forward contact and having a metalized back-side; and
a metallic layer attached to at least a part of the back-side of the chip, wherein the chip is disposed in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and the metallic layer covers at least a part of the top-side of the package module.
13. The integrated circuit package recited in claim 12 wherein the metallic layer is a metal foil layer.
14. The integrated circuit package recited in claim 12 wherein the back-side of the chip has a low ohmic contact.
15. The integrated circuit package recited in claim 14 wherein current flows vertically between the low ohmic contact and the at least one forward contact of the chip.
16. The integrated circuit package recited in claim 14 wherein the low ohmic contact is electrically connected to the metallic layer, and therethrough to one or more vias formed in the package module.
17. The integrated circuit package recited in claim 12 wherein the metallic layer has thermally conductive properties facilitating heat spreading.
18. The integrated circuit package recited in claim 17 wherein the metallic layer is attached to a heat sink.
19. The integrated circuit package recited in claim 12 wherein the chip further comprises through silicon vias.
20. The integrated circuit package recited in claim 12 wherein the metallic layer is coupled to the back-side of the chip or the top-side of the package module by way of an isolating middle layer.
21. A mounted integrated circuit package comprising:
a printed circuit board capable of having an integrated circuit package mounted thereon; and
an integrated circuit package mounted in a reverse mount configuration thereon, the integrated circuit package comprising:
a package module formed from successive build-up layers which define circuit interconnections;
a cavity formed on a top-side of the package module;
a chip having a front-side with at least one forward contact and having a metalized back-side; and
a metallic layer attached to at least a part of the back-side of the chip, wherein the chip is disposed in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and the metallic layer covers at least a part of the top-side of the package module;
wherein a reverse mount configuration is where the metalized back-side of the chip faces towards the printed circuit board and front-side of the chip faces away from the printed circuit board.
22. A mounted integrated circuit package comprising:
a printed circuit board capable of having an integrated circuit package mounted thereon; and
an integrated circuit package mounted in a reverse mount configuration thereon, the integrated circuit package comprising:
a package module formed from successive build-up layers which define circuit interconnections;
a cavity formed on a top-side of the package module;
a chip having a front side with at least one forward contact and having a back-side, the chip disposed in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module; and
a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module;
wherein a reverse mount configuration is where the metalized back-side of the chip faces towards the printed circuit board and front-side of the chip faces away from the printed circuit board.