1. A semiconductor memory cell comprising:
a substrate having a top surface, said substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface;
a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;
a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;
a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type;
a gate positioned between said first and second regions and above said top surface; and
a nonvolatile memory configured to store data upon transfer from said body region.
2. The semiconductor memory cell of claim 1, wherein said nonvolatile memory is further configured to restore data to said body region.
3. The semiconductor memory cell of claim 1, wherein said nonvolatile memory comprises a floating gate or trapping layer positioned in between said first and second regions, above said top surface and below said gate.
4. The semiconductor memory cell of claim 1, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions.
5. The semiconductor memory cell of claim 4, wherein said resistance change element comprises a phase change material.
6. The semiconductor memory cell of claim 4, wherein said resistance change element comprises a metal-oxide-metal system.
7. The semiconductor memory cell of claim 1, wherein nonvolatile memory is configured to store data upon transfer from said body region resulting from an instruction to back up said data stored in said body region.
8. The semiconductor memory cell of claim 1, wherein said transfer from said body region commences upon loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said body region is loaded into and stored in said nonvolatile memory.
9. The semiconductor memory cell of claim 8, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein intentional power loss is predetermined to conserve power.
10. The semiconductor memory cell of claim 8, wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said body region and stored therein.
11. The semiconductor memory cell of claim 10, wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said body region upon said restoration of power.
12. The semiconductor memory cell of claim 11, wherein said cell is configured to reset said nonvolatile memory just prior to writing new data into said nonvolatile memory during a shadowing operation.
13. A semiconductor memory array, including:
a plurality of semiconductor memory cells as recited in claim 1 arranged in a matrix of rows and columns.
14. The semiconductor memory array of claim 13, further comprising a plurality of said matrices vertically stacked and electrically connected to form a three-dimensional array.
15. The semiconductor cell of claim 1, further comprising:
a source line terminal electrically connected to one of said first and second regions;
a bit line terminal electrically connected to the other of said first and second regions;
a word line terminal connected to said gate;
a buried well terminal electrically connected to said buried layer, and
a substrate terminal electrically connected to said substrate below said buried layer.
16. The semiconductor memory cell of claim 15, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions, and wherein one of said source line terminal and said bit line terminal is connected to said resistance change element.
17. The semiconductor memory cell of claim 15, wherein a data state of said body region is maintained by applying a voltage to said substrate terminal.
18. The semiconductor memory cell of claim 17, wherein said voltage applied to said substrate terminal automatically activates said cell when said floating body has a first data state to refresh said first data state, and wherein when said body region of said cell has a second data state, said cell automatically remains deactivated upon application of said voltage to said substrate terminal so that said body region of said cell remains in said second data state.
19. The semiconductor memory cell of claim 17, wherein said substrate terminal is periodically biased by pulsing said substrate terminal with said voltage, and wherein said data state of said body region of said cell is refreshed upon each said pulse.
20. The semiconductor memory cell of claim 17, wherein said substrate terminal is constantly biased by application of said voltage thereto, and said body region constantly maintains said data state.
21. The semiconductor memory cell of claim 1, wherein said first and second regions are formed in a fin that extends above said buried layer, said gate is provided on opposite sides of said fin, between said first and second regions, and said body region is between said first and second regions and between said gate on opposite sides of said fin.
22. The semiconductor memory cell of claim 21, wherein said gate is additionally provided above a top surface of said body region.
23. A semiconductor memory cell comprising:
an arrangement of layers having alternating conductivity types selected from p-type conductivity type and n-type conductivity type configured to function as a silicon controlled rectifier device to store data in volatile memory; and
a nonvolatile memory configured to store data upon transfer from volatile memory.
24. The semiconductor memory cell of claim 23, wherein said silicon controlled rectifier device is provided as a P1-N2-P3-N4 silicon-rectifier device.
25. The semiconductor memory cell of claim 24, wherein said cell comprises:
a substrate having a top surface, said substrate having a p-type conductivity type;
a first region having an n-type conductivity type said first region being formed in said substrate and exposed at said top surface;
a second region having said n-type conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;
a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said n-type conductivity type; and
a body region formed between said first and second regions and said buried layer, said body region having said p-type conductivity type;
wherein said substrate functions as the P1 region of said P1-N2-P3-N4 silicon-rectifier device, said buried layer functions as the N2 region of said P1-N2-P3-N4 silicon-rectifier device, said body region functions as the P3 region of said P1-N2-P3-N4 silicon-rectifier device and said first region or said second region functions as the N4 region of said of P1-N2-P3-N4 silicon-rectifier device.
26. The semiconductor memory cell of claim 25, further comprising a gate positioned between said first and second regions and above said top surface.
27. The semiconductor memory cell of claim 26, wherein said nonvolatile memory comprises a floating gate or trapping layer positioned in between said first and second regions, above said top surface and below said gate.
28. The semiconductor memory cell of claim 26, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions.
29. A method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a nonvolatile memory for storing data, the method comprising:
reading and storing data to the floating body while power is applied to the memory cell;
biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state; and
transferring the data stored in the floating body to the nonvolatile memory when power to the cell is interrupted.
30. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a resistance change element for storing data as non-volatile memory, the method comprising:
reading and storing data to the floating bodies as volatile memory while power is applied to the device;
biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state;
transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the resistance change elements corresponding to the floating bodies, when power to the device is interrupted; and
storing the data in the resistance change elements as non-volatile memory.
31. The method of claim 30, further comprising:
transferring the data stored in the resistance change elements, by a parallel, non-algorithmic, restore process, to the floating bodies corresponding to the resistance change elements, when power is restored to the cell;
and storing the data in the floating bodies as volatile memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A runner for suspended ceilings, the runner being elongated in shape, having a base with two laterally opposite flanges for supporting ceiling tiles and a web hingedly connected to the base between the flanges so as to be foldable between a flat configuration with the web folded against one of the flanges, and an inversed-T configuration with the web normal to the base for suspension and use.
2. The runner of claim 1, wherein the web has a separate component from the base.
3. The runner of claim 2 wherein the web is hingedly connected to the base by a flexible sheet layer adhered to and at least partially covering both one of the flanges and a face of the web.
4. The runner of claim 2 wherein the base has a first flexible sheet layer covering and adhered to a first wood layer, the web has a second wood layer, and a second flexible sheet layer covers both the first flexible sheet layer on one of the flanges of the base, and a face of the web.
5. The runner of claim 4 wherein the first flexible sheet layer and the second flexible sheet layer consist of Kraft paper.
6. The runner of claim 1 wherein the web and the base are formed of a single, integral component having a flexible portion at the base of the web providing the hinged connection between the web and the base.
7. The runner of claim 6 wherein the flexible portion has a smaller thickness than the remainder of the web.
8. The runner of claim 6 wherein the flexible portion has a W-shaped notch defined therein.
9. The runner of claim 6 wherein material constituting the flexible portion is more flexible than a material constituting the remainder of the web.
10. The runner of claim 6 wherein the flexible portion has a longitudinally extending crenate rack.
11. The runner of claim 1 wherein the web has a plurality of regularly longitudinally interspaced apertures on a side thereof away from the base.
12. The runner of claim 11 wherein the apertures are rectangular and flat in the longitudinal direction.
13. The runner of claim 1 wherein both flanges have the same width.
14. The runner of claim 1 in the flat configuration, provided in the form of a coil.
15. A suspended ceiling system having a plurality of runners, each one of the runners having a base with two laterally opposite flanges for supporting ceiling tiles and a web hingedly connected to the base between the flanges.
16. The suspended ceiling system of claim 15 wherein the runners are suspended to a building structure in a grid configuration, with a plurality of parallel and equally interspaced longitudinal runners and a plurality of parallel and equally interspaced transverse runners and an array of intersections therebetween.
17. The suspended ceiling system of claim 16 wherein at each one of the intersections, one of a transverse runner and a longitudinal runner penetrates through the web of and is supported by the base of the other one of a transverse runner and a longitudinal runner.
18. The suspended ceiling system of claim 17 wherein at successive intersections along any one of the longitudinal runners and the transverse runners, an alternating one of a transverse runner and a longitudinal runner penetrates through the web of the other one of a transverse runner and a longitudinal runner.
19. The suspended ceiling system of claim 16, further comprising a plurality of runner connectors, wherein at each one of the intersections, one of the runner connectors lockingly receives the ends of two aligned ones of the longitudinal runners and two aligned ones of the transverse runners.
20. The suspended ceiling system of claim 15 further comprising a plurality of runner connectors, each one of the runner connectors having four runner sockets, oriented at 90\xb0 from one another.
21. The suspended ceiling system of claim 20 wherein the web has a longitudinally extending crenate rack adjacent the base, at least at opposite ends thereof, and each one of the runner sockets also has a crenate rack shaped to mate with the crenate rack of the web in a ratchet configuration which prevents retraction of the runners once they have been inserted into runner sockets.
22. The suspended ceiling system of claim 15 further comprising a plurality of wall brackets having an open-ended slot shaped to securely receive an end of the web of the runners.
23. A method of installing a suspended ceiling comprising unfolding a runner having a web hingedly mounted to a base from a folded configuration where the web is folded against the base, to an unfolded configuration where the web is normal to the base.
24. The method of claim 23, further comprising prior to said unfolding, unrolling the runner from a coiled configuration.
25. The method of claim 23, further comprising affixing an end of the runner to a wall.
26 to 31. (canceled)