1. An optical pulse multiplex unit comprising:
a half mirror for a splitting incident light to produce a transmitted light and a reflected light;
a pair of mirror units arranged on one side and the other side of the half mirror so that the transmitted light and the reflected light split by the half mirror are deflected and are combined again at a common place on the half mirror; and
the mirror unit has a plurality mirrors; and
the mirror unit constructed with a moving mechanism which can be moved along the one direction so that the optical path length can be variable.
2. An optical pulse multiplex unit according to claim 1, wherein there are the N (N is an integer) mirror units and when the reference optical path difference due to a shift of a first mirror unit toward one direction is denoted by \u0394, the substantial optical path difference due to an Nth mirror unit is (2N-1)*\u0394.
3. An optical pulse multiplex unit according to claim 1 or 2, wherein the mirror unit can be moved parallel toward a normal direction of the half mirror by the moving mechanism.
4. An optical pulse multiplex unit according to claim 3, wherein the mirror unit consists of two mirrors.
5. An optical pulse multiplex unit according to claim 2 or 3, wherein the mirror unit consists of four mirrors.
6. An optical pulse multiplex unit comprising:
an half mirror; and
a pair of mirror units arranged on one side and the other side of the half mirror; and
a moving mechanism arranged on one side of the half mirror; and
the mirror unit has at least two mirrors which are arranged to opposite to each other; and
the two mirrors are arranged to decrease the distance between the two mirrors, as they are away from the half mirror; and
the two mirrors and the half mirror are arranged to make a virtual plane which is orthogonal to both the two mirrors and the half mirror; and
the mirror unit is fixed on the moving mechanism.
7. An optical pulse multiplex unit comprising:
a half mirror for a splitting incident light to generate a transmitted light and a reflected light;
a pair of mirror units arranged on one side and the other side of the half mirror so that the transmitted light and the reflected light split by the half mirror are deflected and are combined again at a common place on the half mirror; and
the mirror unit has a plurality of mirrors.
8. An optical pulse multiplex unit according to claim 7, wherein there are the N (N is an integer) mirror units arranged with arbitrary intervals along a normal direction of the half mirror, and when the optical path difference obtained by the mirror unit is denoted by \u0394, the substantial optical path difference owing to an Nth mirror unit is (2N-1)\u0394.
9. An optical pulse multiplex unit according to claim 8, wherein the mirror unit consists of two mirrors.
10. An optical pulse multiplex unit comprising:
an half mirror; and
a pair of mirror units arranged on one side and the other side of the half mirror; and
a moving mechanism arranged on one side of the half mirror; and
the mirror unit has at least two mirrors which are arranged to opposite to each other; and
the two mirrors are arranged to decrease the distance between the two mirrors, as they are away from the half mirror; and
the two mirrors and the half mirror are arranged to make a virtual plane which is orthogonal to both the two mirrors and the half mirror.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A dual gate oxide CMOS integrated circuit, comprising
at least one thin-oxide transistor comprising a thin gate oxide and a first implant type comprising highly-doped, shallow sourcedrain extensions with pockets,
at least one thick-oxide transistor comprising a thick gate oxide and a second implant type, and
at least one further transistor comprising a thick gate oxide and implants comprising highly-doped, shallow sourcedrain extensions with pockets, the at least one further transistor forming a one-time programmable non-volatile memory device.
2. A dual gate oxide CMOS integrated circuit according to claim 1, wherein the one-time programmable non-volatile memory device is arranged to be programmable using Fowler-Nordheim tunneling.
3. A dual gate oxide CMOS integrated circuit according to claim 1, wherein the integrated circuit is fabricated using a CMOS process providing a plurality of different implant doses and wherein the highly-doped, shallow sourcedrain extensions with pockets for the one-time programmable non-volatile memory device are formed using a heaviest implant dose selected from the plurality of different implant doses.
4. A dual gate oxide CMOS integrated circuit according to claim 1, wherein the integrated circuit is fabricated using a CMOS process providing multiple implant steps to form transistors with different threshold voltages and wherein the highly-doped, shallow sourcedrain extensions with pockets for the one-time programmable non-volatile memory device are formed using an implant step producing a highest threshold voltage of all the multiple implant steps.
5. A dual gate oxide CMOS integrated circuit according to claim 1, wherein the integrated circuit is fabricated using a CMOS process providing SVT implants and HVT implants, wherein the highly-doped, shallow sourcedrain extensions with pockets in the one-time programmable non-volatile memory device are formed using HVT implants and wherein the highly-doped, shallow sourcedrain extensions with pockets in the at least one thin-oxide transistor are formed using SVT implants.
6. A dual gate oxide CMOS integrated circuit according to claim 1, wherein each transistor forming a one-time programmable non-volatile memory device comprises two parallel channel areas.
7. A dual gate oxide CMOS integrated circuit according to claim 6, wherein each of the two parallel channel areas has a width close to a minimum feature size supported by a CMOS process used to fabricate the integrated circuit and wherein the two parallel channel areas are separated by a distance close to a minimum spacing supported by the CMOS process.
8. A dual gate oxide CMOS integrated circuit according to claim 1, further comprising at least one further transistor comprising a thin gate oxide and the second implant type.
9. A mask set for the manufacture of a dual gate oxide CMOS integrated circuit, comprising
a first mask for the definition of LDD implants in a thin gate oxide transistor,
a second mask for the definition of a thick gate oxide,
wherein the first mask is open for the definition of LDD implants at a first site and the second mask is open for the definition of a thick gate oxide at that first site, for the formation of a transistor in the integrated circuit at that first site, the transistor formed at that first site comprising a one-time programmable non-volatile memory device.
10. A mask set according to claim 9, further comprising
a third mask for the definition of LDD implants in a thick gate oxide transistor,
wherein the third mask is closed at the first site.
11. A mask set according to claim 10, wherein
the second mask is closed for the definition of a thin gate oxide at a second site and the first mask is open for the definition of LDD implants at that second site, for the formation of a conventional thin-oxide transistor at that site, and
the third mask is open for the definition of LDD implants at a third site and the second mask is open for the definition of a thick gate oxide at that third site, for the formation of a conventional thick-oxide transistor at that site.
12. A mask set according to claim 11, wherein
the third mask is open for the definition of LDD implants at a fourth site and the second mask is closed for the definition of a thin gate oxide at that fourth site, for the formation of a transistor in the integrated circuit at that fourth site.
13. A mask set according to claim 11, wherein the first mask is for the definition of HVT LDD implants in a thin gate oxide transistor.
14. A mask set according to claim 13, further comprising:
a fourth mask for the definition of SVT LDD implants in a thin gate oxide transistor, and
wherein the second mask is closed for the definition of a thin gate oxide at a fifth site and the fourth mask is open for the definition of SVT LDD implants at that fifth site, for the formation of a SVT thin-oxide transistor at that site.
15. A method for the manufacture of a dual-oxide CMOS integrated circuit, comprising the steps of
forming a thin-oxide transistor using a first implant type and a thin oxide configuration, the first implant type comprising highly-doped, shallow sourcedrain extensions with pockets,
forming a thick-oxide transistor using a second implant type and a thick oxide configuration, and
forming a third type of transistor using the thick oxide configuration and the first implant type, the third type of transistor forming a one-time programmable non-volatile memory device.
16. A method for the manufacture of a dual-oxide CMOS integrated circuit according to claim 15, the method of manufacture comprising a plurality of implant doses and the first implant type comprising a heaviest of the plurality of implant doses.
17. A method for the manufacture of a dual-oxide CMOS integrated circuit according to claim 16, the plurality of implant doses comprising SVT and HVT and wherein the highly-doped, shallow sourcedrain extensions with pockets are formed using HVT implants.
18. A method for the manufacture of a dual-oxide CMOS integrated circuit according to claim 17, further comprising:
forming a thin-oxide transistor using a thin oxide configuration and highly-doped, shallow sourcedrain extensions with pockets formed using SVT implants.
19. A method for the manufacture of a dual-oxide CMOS integrated circuit according to claim 15, further comprising the step of forming a fourth type of transistor using the thin oxide configuration and the second implant type.
20. A method for the manufacture of a dual-oxide CMOS integrated circuit according to claim 15, using a mask set comprising:
a first mask for the definition of LDD implants in a thin gate oxide transistor,
a second mask for the definition of a thick gate oxide, and
a third mask for the definition of LDD implants in a thick gate oxide transistor,
and wherein the first mask is open for the definition of LDD implants at a first site, the second mask is open for the definition of a thick gate oxide at that first site and the third mask is closed at the first site for the formation of the third type of transistor in the integrated circuit at that first site.