What is claimed is:
1. A Group III nitride compound semiconductor comprising:
a triple layer structure having an emission layer sandwiched between an n-type cladding layer and a p-type cladding layer;
said emission layer satisfying the formula Alx1Gay1In1-x1-y1N, where 0x11, 0y11, and 0x1y11, and having a thickness larger then diffusion length of holes;
said n-type cladding layer satisfying the formula Alx2Gay2In1-x2-y2N, where 0x21, 0y21and 0x2y21, being doped with a donor impurity, and having a lattice constant substantially equal to a lattice constant of said emission layer: and
said p-type cladding layer satisfying the formula Alx3Gay3In1-x3-y3N, where 0x31, 0y31, and 0x3y31, being doped with an acceptor impurity, having a forbidden band sufficiently wider than a forbidden band of said emission layer to confine electrons injected into said emission layer.
2. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer comprises Gay2In1-y2N, ,where 0.92y21, and wherein said n-type cladding layer comprises gallium nitride (GaN) doped with a donor impurity.
3. The Group III nitride compound semiconductor according to claim 2, wherein said n-type cladding layer is formed on a lower n type layer comprising gallium nitride (GaN), said lower n-type layer being doped with a donor impurity and comprising a donor impurity density higher than a donor impurity density of said n-type cladding layer.
4. The Group III nitride compound semiconductor according to claim 1, wherein said donor impurity is silicon (Si).
5. The Group III nitride compound semiconductor according to claim 1, wherein said acceptor impurity is magnesium (Mg).
6. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer is doped with silicon (Si).
7. The Group III nitride compound semiconductor comprising:
a multiple layer structure including an emission layer sandwiched between an n-type layer and a p-type layer:
said emission layer comprising a semiconductor material satisfying the formula Alx1Gay1In1-x1-y1N, where 0x11, 0y11, and 0x1y11, said emission layer having a thickness significantly larger than a diffusion length of holes within said emission layer:
said n-type cladding layer satisfying the formula Alx2Gay2In1-x2-y2N, where 0x21, 0y21and 0x2y21, being doped with a donor impurity; and
said p-type layer satisfying the formula Alx3Gay3In1-x3-y3N, where 0x31, 0y31, and 0x3y31, being doped with an acceptor impurity.
8. The Group III nitride compound semiconductor according to claim 7, wherein said n-type layer has a lattice constant substantially equal to a lattice constant of said emission layer.
9. The Group III nitride compound semiconductor according to claim 8, wherein said p-type layer comprises a forbidden band sufficiently wider than a forbidden band of said emission layer to confine electrons injected into said emission layer.
10. The Group III nitride compound semiconductor according to claim 1, wherein misfit ratio between said lattice constant of said n-type cladding layer and said lattice constant of said emission layer is within 1%.
11. The Group III nitride compound semiconductor according to claim 8, wherein misfit ratio between said lattice constant of said n-type cladding layer and said lattice constant of said emission layer is within 1%.
12. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer has a thickness of 0.1 m to 1.0 m.
13. The Group III nitride compound semiconductor according to claim 7, wherein said emission layer has a thickness of 0.1 m to 1.0 m.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit chip, comprising:
a plurality of trenches at least partially surrounding a perimeter of a critical portion of the integrated circuit chip;
circuitry sensitive to temperature variation located in said critical portion;
wherein said trenches are locally disconnected from each other;
one or more electrical connections passing along a portion of the integrated circuit chip where the trenches are locally disconnected from each other, said electrical connections extending between said critical portion and an outer portion of the integrated circuit chip;
one or more heating resistors placed in said circuit portion; and
a temperature sensor placed in said circuit portion.
2. The chip of claim 1, wherein the temperature sensor is a PN junction diode.
3. The chip of claim 1, wherein the heating resistors are diffused resistors.
4. The chip of claim 1, wherein said plurality of trenches comprises a double network of trenches surrounding the critical portion, the trenches of said double network of trenches being formed to define arms connecting the critical portion of the integrated circuit ship to the outer portion of the integrated circuit chip.
5. The chip of claim 1, comprising a semiconductor layer supported by, but insulated from, an underlying support layer, wherein said trenches extend to a depth which passes completely through a thickness of the semiconductor layer.
6. The chip of claim 1, wherein a bottom of said critical portion is insulated from said underlying support layer.
7. The chip of claim 1, further comprising a cap layer mounted to the outer portion of the integrated circuit chip and extending over, but insulated from, said critical portion.
8. The chip of claim 1, comprising an amplifier including a first circuit part in the outer portion of the integrated circuit chip and a second circuit part which comprises said circuitry sensitive to temperature variation in the critical portion.
9. The chip of claim 8, wherein said circuitry sensitive to temperature variation affects offset voltage of the amplifier.
10. The chip of claim 8, wherein said second circuit part which comprises said circuitry sensitive to temperature variation comprises an input stage of said amplifier.
11. A method, comprising:
defining a critical portion of an integrated circuit chip;
providing a plurality of insulating trenches at least partially surrounding a perimeter of the critical portion;
placing circuitry that is sensitive to temperature variation within the critical portion;
placing a temperature sensor within the critical portion placing heating resistor elements in critical portion.
12. The method of claim 11, further comprising:
actuating the heating resistors to subject the critical portion to temperature variation;
monitoring the temperature sensor in response to said temperature variation so as to test the integrated circuit chip at various temperatures; and
adjusting said circuitry that is sensitive to temperature variation.
13. The method of claim 11, wherein the temperature sensor is a PN junction diode.
14. The method of claim 11, wherein providing said plurality of trenches comprises forming a double network of trenches surrounding the critical portion, the trenches of said double network of trenches being formed to define arms connecting the critical portion of the integrated circuit ship to an outer portion of the integrated circuit chip.
15. The method of claim 11, further comprising forming one or more electrical connections passing along a portion of the integrated circuit chip where the trenches are locally disconnected from each other, said electrical connections extending between said critical portion and an outer portion of the integrated circuit chip.
16. The method of claim 15, further comprising mounting a cap layer to the outer portion of the integrated circuit chip and extending over, but insulated from, said critical portion.
17. The method of claim 11, wherein providing said plurality of insulating trenches comprises extending each of said wherein said trenches to a depth which passes completely through a thickness of a semiconductor layer that is supported by, but insulated from, an underlying support layer.
18. The method of claim 11, further comprising integrating an amplifier circuit for said integrated circuit chip including a first circuit part formed in an outer portion of the integrated circuit chip and a second circuit part which comprises said circuitry sensitive to temperature variation in the critical portion.
19. The method of claim 18, wherein said circuitry sensitive to temperature variation affects offset voltage of the amplifier.
20. The method of claim 18, wherein said second circuit part which comprises said circuitry sensitive to temperature variation comprises an input stage of said amplifier.
21. The method of claim 11, wherein said plurality of insulating trenches are locally disconnected from each other.