What is claimed is:
1. An imaging device for imaging radiation, said imaging device comprising an array of pixel cells having a semiconductor substrate including an array of pixel detectors which generate charge in response to incident radiation and a corresponding array of pixel circuits, each pixel circuit being associated with a respective pixel detector for accumulating charge resulting from radiation incident on said pixel detector, said pixel circuits being individually addressable and comprising circuitry for accumulating charge from successive radiation hits on the respective pixel detectors.
2. An imaging device according to claim 1, wherein each pixel circuit comprises a charge storage device for accumulating charge.
3. An imaging device according to claim 2 wherein the capacitance of said charge storage device forms substantially the input node capacitance of said pixel circuit and of said pixel cell.
4. An imaging device according to claim 2, wherein each pixel circuit comprises at least two transistors, a first transistor acting as said charge storage device and a second transistor acting as a readout switch, being responsive to an enable signal to connect said first transistor to an output line for outputting any accumulated charge.
5. An imaging device according to claim 2, wherein each pixel circuit comprises at least two transistors in a cascade amplifier stage.
6. An imaging device according to claim 4, wherein said transistors are field effect transistors.
7. An imaging device according to claim 6, wherein the FET capacitance of the first transistor substantially forms the input node capacitance of the pixel circuit and of said pixel cell.
8. An imaging device according to claim 4, wherein each pixel circuit comprises a further field effect transistor responsive to a reset signal to reset said charge storage device.
9. An imaging device according to claim 2, wherein the pixel circuit comprises overload protection circuitry, preferably diodes, for over and under voltage protection.
10. An imaging device according to claim 1 comprising electrical resistance means for electrically separating pixel cells.
11. An imaging device according to claim 10 wherein said electrical resistance means comprises a non-conductive passivation layer between adjacent pixel detectors.
12. An imaging device according to claim 11, wherein a potential is applied to said passivation layer to create a potential barrier within said semiconductor substrate under said passivation layer for further electrically separating pixel cells.
13. An imaging device according to claim 10, wherein said electrical resistance means comprises a diode formed as part of said pixel circuit.
14. An imaging device according to claim 10, wherein said electrical resistance means comprises a bipolar transistor formed as part of said pixel circuit.
15. An imaging device according to claim 14, wherein a base of said bipolar transistor for each pixel circuit is set to a common potential.
16. An imaging device according to claim 1. wherein the charge value accumulated in a pixel circuit is output from a pixel circuit as a current value.
17. An imaging device according to claim 1, wherein said pixel cell size is of the order of or less than 1 mm across, preferably approximately 350 m across.
18. An imaging device according to claim 1, wherein said pixel cell size is approximately 150 m across or less, preferably approximately 50 m across or less and more preferably approximately 10 m across.
19. An imaging device according to claim 1, wherein said substrate is between 200 m and 3 mm thick.
20. An imaging device according to claim 1, wherein said pixel circuits are integral to said substrate and aligned with the corresponding pixel detectors.
21. An imaging device according to claim 1, wherein said pixel circuits are formed in a further substrate, said further substrate incorporating said pixel circuits being coupled to said substrate incorporating said pixel detectors, with each pixel circuit being aligned with and being coupled to the corresponding pixel detector.
22. An imaging device according to claim 1 wherein said array comprises a single row of pixel detectors and associated pixel circuits forming a slit-shaped imaging device or a plurality of rows of pixel detectors and associated pixel circuits forming a slot-shaped imaging device.
23. An imaging device according to claim 22 wherein said pixel circuits for respective pixel detectors are laterally adjacent to the corresponding pixel detectors.
24. An imaging device according claim 1 wherein charge can be accumulated on each pixel circuit for a period of up to the order of a second before readout.
25. An imaging device according to claim 1 including control electronics including addressing logic for addressing individual pixel circuits for reading accumulated charge values from said pixel circuits and selectively resetting said pixel circuits.
26. An imaging device according to claim 25, wherein said addressing logic comprises means for connecting output lines of said pixels circuits to an output of said imaging device, means for supplying read enable signals to read enable inputs of said pixel circuits and means for supplying reset signals to reset inputs of said pixel circuits.
27. An imaging device according to claim 26 wherein said means for connecting output lines comprises a shift register or a counter for sequentially connecting output lines of said pixel circuits for respective columns of pixels to said output of said imaging device.
28. An imaging device according to claim 26 wherein said means for supplying read enable signals comprises a shift register or a counter for sequentially supplying read enable signals to read enable inputs of said pixel circuits for respective rows of pixels.
29. An imaging device according to claim 27 wherein said means for supplying reset signals comprises a shift register or a counter for sequentially supplying reset signals to reset inputs of said pixel circuits for respective rows of pixels.
30. An imaging device according to claim 25, wherein said control electronics includes an analogue to digital converter for converting an analogue charge value from a said pixel circuit into a digital charge value.
31. An imaging device according to claim 25, wherein at least part of said control electronics is integrated into a semiconductor substrate on which said pixel circuits are integrated.
32. An imaging device according to claim 1, wherein the semiconductor substrate is made of a material selected from: CdZnTe, CdTe, HgI2, InSb, GaAs, Ge, TlBr and Si.
33. An imaging system comprising an imaging device according to claim 30, said imaging device comprising an image processor connected to said control electronics for processing said digital charge values from respective pixel circuits to form an image for display on a display device.
34. An imaging system according to claim 33, wherein said processor determines maximum and minimum charge values for pixels for display, assigns extreme grey scale or colour values to said maximum and minimum charge values and allocates grey scale or colour values to an individual pixel according to a sliding scale between said extreme values in dependence upon the charge value for said pixel.
35. An imaging system according to claim 34, wherein said grey scale or colour values are allocated in accordance with the following formula:
3
Grey
scale
value
of
pixel
i
=
Min
grey
+
(
i
charge
–
Min
charge
)
(
Max
charge
–
Min
charge
)
(
Max
grey
–
Min
grey
)
.
36. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic.
37. An imaging system according to claim 36 wherein said mosaic comprises a plurality of columns of tiled imaging devices, said imaging devices of adjacent columns being offset in the column direction.
38. An imaging system according to claim 36 comprising means for stepping or moving said imaging device andor an object to be imaged to accumulate an image over a complete image area.
39. An imaging system according to claim 36 comprising two imaging surfaces, each comprising a mosaic of imaging devices, said imaging surfaces being arranged substantially parallel to one another and spaced from one another with an object to be imaged between said surfaces, the mosaics being offset laterally with respect to one another to give substantially complete imaging of said object.
40. An imaging system comprising a plurality of imaging devices according to claim 1 wherein said imaging devices are arranged substantially tangentially around the periphery of a ring or part-ring to encircle or partially encircle a slice of an object to be imaged by, for example, a computerized tomography technique.
41. An imaging system according to claim 40, wherein said imaging devices are arranged substantially tangentially around the periphery of a plurality of rings or part-rings displaced from one another in the direction forming a common axis of said rings or part-rings.
42. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic matching the area and shape of an object to be imaged.
43. An imaging system comprising a plurality of imaging devices according to claim 1 tiled together to form a mosaic surrounding part or all of an object to be imaged.
44. An imaging system according to claim 36, wherein respective image outputs of a plurality of tiled imaging devices are connected to a common multiplexer, the output of which multiplexer is connected to a common analogue to digital converter.
45. An imaging system according to claim 36, wherein respective image outputs of a plurality of tiled imaging devices are daisy-chained to a common analogue to digital converter.
46. An imaging system according to claim 44, wherein the output of said multiplexer comprises current values representative of accumulated charge from said pixel circuits.
47. An imaging system according to claim 33, wherein individual pixel circuits are addressed for reading accumulated charge at a rate to optimize the resolution of an analogue to digital converter for converting analogue accumulated charge values into digital values.
48. An imaging system according to claim 33, wherein multiple image frames are accumulated, either at an analogue to digital conversion stage, or subsequently at an image processing stage.
49. An imaging system according to claim 33 arranged to accumulate image frames at said pixel cells, to repeatedly read out a refresh image for display and to reset said pixel circuits at a rate sufficient to avoid saturation of a charge storage device of said pixel circuits.
50. An imaging system comprising one or more slit- or slot-shaped imaging device(s) according to claim 22 and means for relative movement between said slit- or slot-shaped imaging device(s) and an object to be imaged in a direction transversely to a longitudinal axis of said imaging device(s) for accumulating a complete image over an imaging area.
51. A method of operating an imaging system according to claim 50 comprising providing relative movement between said slit- or slot- shaped imaging device(s) and an object to be imaged in said transverse direction and reading accumulated charge from said pixel circuits of said slit- or slot-shaped imaging device(s) at a rate corresponding to said movement by half or less than half of the pixel size in the direction of motion.
52. A method of operating an imaging system comprising one or more slit- or slot-shaped imaging devices according to claim 22 comprising minimizing the effect of scattered radiation by optimizing the relationship between the following parameters: the distance between a radiation source and an object to be imaged; the distance between the object to be imaged and the slit- or slot-shaped imaging device(s); and the width of the slit- or slot-shaped imaging device(s).
53. A method for imaging accumulated values corresponding to respective pixel positions within a pixel array, such as, for example, charge values accumulated for respective pixel positions of an imaging device according to claim 1, said method comprising:
determining maximum and minimum accumulated values for pixels within an area of said pixel array to be imaged;
assigning grey scale or colour values at extremes of a grey or colour scale to be imaged to said maximum and minimum accumulated values; and
assigning grey scale or colour values to said accumulated values for individual pixels scaled in accordance with said extreme values; and
imaging said assigned grey scale or colour values at respective image pixel positions.
54. A method for automatically detecting and eliminating detected pixel value representative of radiation incident on a pixel detector of an imaging device, for example an imaging device according to claim 1, said method comprising:
comparing said detected pixel value to a threshold value related to a minimum detected charge value expected for directly incident radiation; and
discarding detected pixel values less than said threshold value.
55. A method of automatically optimizing imaging using, for example, an imaging system according to claim 33 for different imaging applications where incident radiation leaves a different electrical signal in a pixel detector of a semiconductor substrate dependent on a semiconductor material or compound used and an energy and a type of incident radiation, said method comprising:
determining an expected best resolution using a centre of gravity technique;
determining an expected efficiency as a function of radiation type and energy; and
either determining a pixel size and thickness as a function of a selected radiation type and energy and a selected semiconductor material or compound or determining the best semiconductor choice for a given radiation type and energy as a function of the achieved resolution and efficiency.
56. A method according to claim 55 comprising automatically selecting an imaging device having said determined pixel size and thickness.
57. A method for performing real time imaging of an organic or inorganic object, said method comprising:
irradiating said object using a radiation source that produces X-rays, -rays, -rays or -rays;
detecting at a semiconductor imaging plane or planes of an imaging device according to claim 1 unabsorbed radiation or radiation that is emitted from selected areas of said object, whereby the amount of charge resulting from radiation incident successively on respective pixel detectors of said imaging device is accumulated in respective pixel circuits:
addressing said pixel circuits individually for reading out accumulated charge;
processing said read out charge to provide image pixel data; and
displaying said image pixel data.
58. A method of operating an imaging device according to claim 1, the method comprising:
reading the accumulated charge from individual pixel circuits at a rate to optimize the resolution of an analogue to digital converter for converting analogue accumulated charge values into digital values.
59. Use of an imaging device according to claim 1 for conventional X-rays, for chest X-rays, for X-ray mammography, for X-ray tomography, for computerized tomography, for spiral computerized tomography, for X-ray bone densiometry, for -ray nuclear radiography, for gamma cameras for single photon emission computerized tomography (SPECT), for positron emission tomography (PET), for X-ray dental imaging, for X-ray panoramic dental imaging, for -ray imaging using isotopes for DNA, RNA and protein sequencing, hybridization in situ, hybridization of DNA, RNA and protein isolated or integrated and generally for -ray imaging and autoradiography using chromatography and polymerars chain reaction, for X-ray and -ray imaging in product quality control, for non-destructive testing and monitoring in realtime and online, and for security control systems.
60. Use of an imaging device according to claim 1 for infrared imaging, optical light imaging or ultraviolet light imaging.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a semiconductor device, comprising:
forming a storage node contact plug over a cell region of a substrate;
forming a first inter-layer dielectric layer over the substrate;
forming a first bit line over the first inter-layer dielectric layer in a peripheral region of the substrate;
forming a second inter-layer dielectric layer over the first inter-layer dielectric layer;
forming a second bit line over the second inter-layer dielectric layer in the peripheral region and electrically coupled to the first bit line;
etching the second inter-layer dielectric layer to expose an upper surface of the storage node contact plug in the cell region;
forming a capacitor in contact with the storage node contact plug in the cell region;
forming a third inter-layer dielectric layer over the substrate having the capacitor formed thereon;
forming a metal contact through the third inter-layer dielectric layer to contact the second bit line in the peripheral region; and
forming a metal line in contact with the metal contact over the third inter-layer dielectric layer.
2. The method of claim 1, wherein the forming of the metal contact comprises:
forming a contact hole exposing the second bit line by selectively etching the third inter-layer dielectric layer in the peripheral region; and
forming the metal contact by filling the contact hole with a conductive material.
3. The method of claim 1, wherein the forming of the second bit line comprises:
forming a bit line contact plug through the second inter-layer dielectric layer to contact the first bit line; and
forming the second bit line over the second inter-layer dielectric layer and in contact with the bit line contact plug.
4. The method of claim 1, wherein the upper surface of the storage node contact plug is exposed through a dry etch process, a wet etch process, or a combination of a dry etch process and a wet etch process.
5. The method of claim 1, wherein the forming of the capacitor comprises:
forming an etch stop layer over the substrate having the storage node contact plug formed in the cell region;
forming a mold layer over the etch stop layer;
performing a planarization process until a portion of the etch stop layer is exposed;
forming a storage node hole exposing the upper surface of the storage node contact plug by selectively etching the mold layer and the etch stop layer;
forming a storage node inside the storage node hole;
removing the mold layer;
forming a dielectric layer along the surface of the storage node; and
forming a plate electrode covering the storage node.
6. The method of claim 5, wherein the selective etching used in the forming of the storage node hole is an etch process that uses fluorocarbon gas.
7. The method of claim 6, wherein in addition to the fluorocarbon gas, the etch process uses one or more gases selected from the group consisting of fluoromethane gas, carbonyl sulfide, oxygen, tetrachlorosilane, and methane.
8. The method of claim 7, wherein the etch process further uses an inert gas.
9. The method of claim 5, wherein the storage node is a cylindrical type or a pillar type.
10. The method of claim 5, wherein the mold layer is a flexible dielectric layer.
11. The method of claim 1, wherein the forming of the capacitor comprises:
forming an etch stop layer over the substrate having the storage node contact plug formed in the cell region;
forming a first mold layer over the etch stop layer;
performing a planarization process until a portion of the etch stop layer is exposed;
forming a first storage node hole exposing the upper surface of the storage node contact plug by selectively etching the first mold layer and the etch stop layer;
forming a first storage node inside the storage node hole;
forming a second mold layer over the first mold layer;
forming a second storage node hole exposing an upper surface of the first storage node by selectively etching the second mold layer;
forming a second storage node inside the second storage node hole;
removing the first mold layer and the second mold layer;
forming a dielectric layer along the surface of the first storage node and the second storage node; and
forming a plate electrode covering the first storage node and the second storage node.
12. The method of claim 11, wherein the first storage node is a pillar type.
13. The method of claim 11, wherein the second storage node is a pillar type or a cylindrical type.
14. The method of claim 11, wherein the first mold layer and the second mold layer are formed of the same material.
15. The method of claim 11, wherein the first mold layer and the second mold layer comprise a flexible dielectric layer.
16. The method of claim 1, further comprising:
forming a first etch stop layer between forming the first inter-layer dielectric layer and forming the second inter-layer dielectric layer.
17. The method of claim 1, wherein the etching of the second inter-layer dielectric layer comprises:
forming a mask in the peripheral region; and
etching the second inter-layer dielectric layer.
18. The method of claim 17, wherein the mask protects the second bit line in the peripheral region from being damaged by the etching of the second inter-layer dielectric layer.
19. The method of claim 1, further comprising:
forming a peripheral gate over the substrate in the peripheral region; and
forming a first bit line contact plug,
wherein the peripheral gate is electrically connected to the first bit line via the first bit line contact plug.