1. A method for manufacturing a sensor support member, the sensor support member fixing a capacitance sensor, which detects a conductive object existing between an opening and closing body actuated by a drive portion and an edge of an opening, either to a closing end of the opening and closing body that is on the leading side when the opening and closing body is being closed or to the edge of the opening, wherein the capacitance sensor includes a conductive sensor electrode, wherein the capacitance sensor outputs a detection signal that corresponds to the capacitance between the sensor electrode and a conductive object located close to the sensor electrode, and wherein the sensor support member includes a guard electrode made of conductive resin material, the voltage of the guard electrode being maintained either at the same level as the voltage of the sensor electrode or at a level of a constant ratio relative to the voltage of the sensor electrode, the manufacturing method comprising:
providing the sensor supporting member with a holding portion, which holds the capacitance sensor, and an attaching portion, which fixes the holding portion either to the closing end or to the edge of the opening, the attaching portion having a main body made of insulating resin material;
forming a flat reinforcing plate from a conductive plate;
embedding at least a part of the reinforcing plate in the guard electrode, thereby integrating the reinforcing plate with the guard electrode;
bending the reinforcing plate integrated with the guard electrode, thereby forming a conductive reinforcing member; and
embedding the reinforcing member in the main body after the reinforcing member is formed.
2. The manufacturing method according to claim 1, further comprising:
causing the holding portion to hold the capacitance sensor at the same time as the reinforcing member integrated with the guard electrode is embedded in the main body.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a semiconductor device, comprising:
forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a sacrificial gate electrode layer over a sacrificial gate dielectric layer;
forming sidewall spacers on both sides of the dummy gate structure;
performing a deep pre-amorphization implant;
performing an ion implantation to form heavily doped sourcedrain regions in the semiconductor substrate;
removing the sidewall spacers;
after removing the sidewall spacers, forming a stress material layer over the dummy gate structure;
performing an annealing process;
after the annealing process, removing the stress material layer;
forming an interlayer dielectric layer surrounding the dummy gate structure;
removing the dummy gate structure to form a groove in the interlayer dielectric layer;
forming a high-k dielectric layer and a metal gate structure in the groove;
forming contact holes that expose at least part of the heavily doped sourcedrain regions; and
forming a self-aligned silicide over exposed portions of the heavily doped sourcedrain regions.
2. The method of claim 1, wherein the high-k dielectric layer comprises one or more of hafnium oxide, hafnium silicon oxide, silicon oxynitride, hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium, or alumina.
3. The method of claim 1, wherein the sacrificial gate dielectric layer comprises an oxide material, and the sacrificial gate electrode layer comprises polysilicon or amorphous carbon.
4. The method of claim 1, wherein an interface layer is formed below the high-k dielectric layer, the interface layer comprising silicon oxide.
5. The method of claim 1, further comprising forming a covering layer between the high-k dielectric layer and the metal gate structure, the covering layer comprising titanium nitride or tantalum nitride.
6. The method of claim 1, further comprising forming offset spacers between the dummy gate structure and the sidewall spacers, wherein the offset spacers comprise an oxide material and the sidewall spacers comprise silicon nitride.
7. The method of claim 6, wherein the stress material layer is formed over the offset spacers.
8. The method of claim 6, further comprising an ion implantation step for forming lightly doped sourcedrain regions in said semiconductor substrate before forming the sidewall spacers.
9. The method of claim 8, wherein the pre-amorphization implant is carried out before forming the lightly doped sourcedrain regions.
10. The method of claim 9, wherein the pre-amorphization implant includes implanting group IV ions.
11. The method of claim 8, further comprising performing an ion implantation to form pocket regions surrounding the lightly doped sourcedrain regions.
12. The method of claim 1, wherein a conformal deposition process is used to form the stress material layer.
13. The method of claim 1, wherein forming the interlayer dielectric layer surrounding the dummy gate structure comprises:
forming a contact hole etch stop layer;
forming the interlayer dielectric layer; and
polishing the interlayer dielectric layer to expose the dummy gate structure.
14. The method of claim 13, wherein the contact hole etch stop layer comprises a silicon nitride material, and the interlayer dielectric material comprises a silicon oxide material.
15. The method of claim 1, wherein the metal gate structure comprises a work function setting metal layer, a barrier material layer, and a metal gate electrode material layer.
16. The method of claim 15, wherein the work function setting metal layer comprises one or more layers of metal or metal compound, and the barrier material layer comprises titanium nitride or tantalum nitride.
17. The method of claim 1, further comprising, before forming the contact holes, forming a second interlayer dielectric layer overlying the metal gate structure, and planarizing the second interlayer dielectric layer.
18. A method of manufacturing a semiconductor device, comprising:
forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a sacrificial gate electrode layer over a sacrificial gate dielectric layer;
forming offset spacers on both sides of the dummy gate structure, and performing an ion implantation to form lightly doped sourcedrain regions in the semiconductor substrate;
forming sidewall spacers on both sides of the dummy gate structure, and performing an ion implantation to form heavily doped sourcedrain regions in the semiconductor substrate;
removing the sidewall spacers;
after removing the sidewall spacers, forming a stress material layer over the dummy gate structure and the offset spacers;
performing an annealing process;
after the annealing process, removing the stress material layer;
forming a planarized dielectric layer surrounding the dummy gate structure and exposing a top surface of the dummy gate structure;
removing the dummy gate structure to form a groove in the planarized dielectric layer;
forming a high-k dielectric layer and a metal gate structure in the groove;
forming contact holes that expose at least part of the heavily doped sourcedrain regions; and
forming a self-aligned silicide over exposed portions of the heavily doped sourcedrain regions.
19. The method of claim 18, wherein the metal gate structure comprises a work function setting metal layer, a barrier material layer, and a metal gate electrode material layer.
20. The method of claim 18, further comprising, before forming the contact holes, forming a second interlayer dielectric layer overlying the metal gate structure, and planarizing the second interlayer dielectric layer.