1. A method comprising:
expanding a threshold voltage read range of a multilevel memory cell without using a negative voltage pump; and
applying a boost voltage to an output of a sense amplifier.
2. The method of claim 1 including applying a positive voltage to read the cell.
3. The method of claim 2 including pre-charging a bitline.
4. The method of claim 1 including applying a voltage to said cell using a buffer.
5. The method of claim 4 including correcting for a non-ideal characteristics of said buffer.
6. The method of claim 5 including subtracting a voltage on a source of the selected cell from a source reference voltage to create a difference.
7. The method of claim 6 including adding the difference to a reference voltage applied to said buffer.
8. The method of claim 1 including providing a bitline voltage generator to create a reference voltage applied to a sense amplifier.
9. The method of claim 8 including developing a current in said generator that is equal to a bitline clamp voltage applied to said generator divided by a first resistance in said generator, said reference voltage to said sense amplifier being equal to the bitline clamp reference voltage times a ratio of a second resistance to said first resistance plus a source voltage on said cell.
10. An apparatus comprising:
a multilevel memory cell having a source, drain, and gate;
a buffer to supply a word line voltage to the gate of said cell;
a bias circuit to apply a positive voltage to the source of said cell during reading; and
a subtracter coupled to the source of said cell, said subtracter to subtract a source reference voltage from a voltage of said source and to apply the difference to an adder, said adder coupled to said buffer.
11. The apparatus of claim 10 including a circuit to correct for non-ideal characteristics of a buffer coupled to the gate of said multilevel cell.
12. The apparatus of claim 10 including a sense amplifier coupled to the drain of said cell, said sense amplifier having an output coupled through a capacitor to a boost voltage, said boost voltage applied to a bitline when reading a cell on said bitline.
13. The apparatus of claim 12 including an inverter coupled to said capacitor, said boost voltage being sufficient to enable said inverter to switch when the cell is conducting even with said positive voltage applied to its source.
14. The apparatus of claim 12 including a bitline clamp generator coupled to said sense amplifier, said sense amplifier being a cascode transistor.
15. The apparatus of claim 14, said bitline clamp generator to supply a reference voltage to the gate of said cascode transistor that is equal to a ratio of resistances of resistors in said bitline clamp generator times a reference voltage applied to said bitline clamp generator plus the source voltage on said cell.
16. A method comprising:
reading a multilevel cell using a sense amplifier; and
applying a boost voltage to an output of said sense amplifier to enable an inverter coupled to said sense amplifier to shift, a source of a selected cell being biased so that without said boost voltage, the inverter will not switch when reading a conducting cell.
17. The method of claim 16 including applying a voltage to a gate of the cell using a buffer and correcting for a non-ideal characteristic of said buffer.
18. The method of claim 17 including subtracting a voltage on the source of a selected cell from a source reference voltage to create a difference and adding the difference to a reference voltage applied to said buffer.
19. The method of claim 16 including providing a bitline voltage generator to create a reference voltage applied to said sense amplifier.
20. The method of claim 19 including developing a current in said generator that is equal to a bitline clamp voltage applied to said generator divided by a first resistance in said generator, said reference voltage to said sense amplifier being equal to the bitline clamp reference voltage times a ratio of a second resistance to said first resistance plus the source voltage on said cell.
21. An apparatus comprising:
a non-volatile memory cell having a gate, source, and drain;
a buffer coupled to the gate of said cell; and
a circuit coupled to said cell and said buffer to correct for a non-ideal characteristic of said buffer.
22. The apparatus of claim 21, said circuit including a subtracter coupled to said source, said subtracter to subtract a source reference voltage from said source voltage and to apply the difference to an adder, said adder coupled to the input of said buffer.
23. The apparatus of claim 22, said drain coupled to a bitline, said bitline coupled to a cascode transistor.
24. The apparatus of claim 23 including a capacitor coupled to the sense amplifier output, said sense amplifier output coupled to a boost voltage, said sense amplifier coupled to an inverter, said boost voltage to switch said inverter when said cell is conducting.
25. The apparatus of claim 21 wherein said cell is a flash cell.
26. The apparatus of claim 25 wherein said cell is a NAND flash cell.
27. The apparatus of claim 21 wherein said cell is a phase change memory cell.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fin-type field effect transistor (FinFET) comprising:
a fin;
a first gate conductor on a first sidewall of said fin;
a second gate conductor on a second sidewall of said fin; and
an insulator on a top side of said fin electrically separating said first gate conductor from said second gate conductor,
wherein said first gate conductor and said second gate conductor each comprise:
a first conductive layer on said first sidewall and said second sidewall; and,
a second conductive layer on said first conductive layer and on said top side of said fin, and
wherein said insulator comprises an oxidized portion of said second conductive layer on said top side of said fin.
2. The FinFET in claim 1, wherein portions of said first sidewall and said second sidewall comprise a gate dielectric corresponding to a central channel region of said fin and wherein said first conductive layer comprises a conductive sidewall spacer on said gate dielectric and said second conductive layer comprises a conductive material capable of being converted into an insulating material.
3. The FinFET in claim 2, wherein said conductive material capable of being converted into an insulating material comprises a different conductive material from said first conductive layer.
4. The FinFET in claim 2, wherein said conductive material capable of being converted into an insulating material comprises an implanted outer surface of said first conductive layer.
5. The FinFET in claim 4, wherein said implanted outer surface of said first conductive layer is implanted with germanium in sufficient concentrations to enhance the oxidation rate of said outer surface thereby converting said outer surface into said conductive material capable of being converted into an insulating material.
6. A fin-type field effect transistor (FinFET) comprising:
a fin having a central channel region and end portions, said end portions comprising source and drain regions;
a first gate conductor on a first sidewall of said fin;
a second gate conductor on a second sidewall of said fin; and
an insulator on a top side of said fin electrically separating said first gate conductor from said second gate conductor,
wherein said first gate conductor and said second gate conductor each comprise:
a first conductive layer on said first sidewall and said second sidewall; and,
a second conductive layer on said first conductive layer and on said top side of said fin, wherein said second conductive layer comprises silicon germanium, and
wherein said insulator comprises an oxidized portion of said second conductive layer on said top side of said fin.
7. The FinFET in claim 6, wherein portions of said first sidewall and said second sidewall comprise a gate dielectric corresponding to a central channel region of said fin and wherein said first conductive layer comprises a conductive sidewall spacer on said gate dielectric.
8. The FinFET in claim 6, wherein said conductive material capable of being converted into an insulating material comprises a different conductive material from said first conductive layer.
9. The FinFET in claim 6, wherein said conductive material capable of being converted into an insulating material comprises an implanted outer surface of said first conductive layer.
10. The FinFET in claim 9, wherein said implanted outer surface of said first conductive layer is implanted with germanium in sufficient concentrations to enhance the oxidation rate of said outer surface thereby converting said outer surface into said conductive material capable of being converted into an insulating material.
11. A fin-type field effect transistor (FinFET) comprising:
an oxide layer;
a fin on said oxide layer;
a first gate conductor on a first sidewall of said fin;
a second gate conductor on a second sidewall of said fin;
a first insulator on a top side of said fin;
a second insulator on said top side of said fin above said first insulator,
wherein said second insulator electrically separates said first gate conductor from said second gate conductor, and
wherein said first gate conductor and said second gate conductor each comprise:
a first conductive layer on said first sidewall and said second sidewall;
a second conductive layer distinct from said first conductive layer having first portions on said first conductive layer and a second portion on said first insulator, wherein said second portion is oxidized and comprises said second insulator; and
a third conductive layer distinct from said first conductive layer and said second conductive layer on said first portions of said second conductive layer and not above said second insulator, wherein a first top surface of said third conductive layer is approximately level with a second top surface of said second portion;
an insulating layer on said third conductive layer and on said second insulator;
a first contact opening through said insulating layer to said first gate conductor; and
a second contact opening through said oxide layer to said second gate conductor.
12. The FinFET in claim 11, wherein portions of said first sidewall and said second sidewall comprise a gate dielectric corresponding to a central channel region of said fin and wherein said first conductive layer comprises a conductive sidewall spacer on said gate dielectric.
13. The FinFET in claim 11, wherein said second conductive layer comprises a different conductive material from said first conductive layer.
14. The FinFET in claim 11, wherein said second conductive layer comprises a conductive material that is capable of being converted into an insulating material.
15. The FinFET in claim 11, wherein said second conductive layer comprises an implanted outer surface of said first conductive layer.
16. The FinFET in claim 15, wherein said implanted outer surface of said first conductive layer is implanted with germanium in sufficient concentrations to enhance the oxidation rate of said outer surface thereby converting said outer surface into a conductive material capable of being converted into an insulating material.
17. A fin-type field effect transistor (FinFET) comprising:
an oxide layer;
a fin on said oxide layer;
a first gate conductor on a first sidewall of said fin;
a second gate conductor on a second sidewall of said fin, wherein said first gate conductor and said second gate conductor are taller than said fin;
an insulating layer above said first gate conductor and said second gate conductor and between said first gate conductor and said second gate conductor on a top side of said fin such that said insulating layer electrically separates said first gate conductor from said second gate conductor,
wherein said first gate conductor and said second gate conductor each comprise multiple conductive layers;
a first contact opening through said insulating layer to said first gate conductor; and
a second contact opening through said oxide layer to said second gate conductor.
18. The FinFET in claim 17, wherein portions of said first sidewall and said second sidewall comprise a gate dielectric corresponding to a central channel region of said fin and wherein said first gate conductor and said second gate conductor each comprise a first conductive layer comprising a conductive sidewall spacer on said gate dielectric.
19. The FinFET in claim 18, wherein said first gate conductor and said second gate conductor each further comprise a second conductive layer comprising a different conductive material from said first conductive layer.