1. A method for manufacturing a non-volatile memory structure, comprising:
providing a substrate comprising an active area and an isolation structure surrounding the active area, wherein the active area comprises a pair of predetermined sourcedrain regions and a middle region therebetween;
forming a first gate and a second gate on the substrate and opposite each other, such that at least one portion of the middle region of the active area is between the first gate and the second gate;
forming an dielectric layer conformally on the substrate;
forming a charge-trapping layer conformally on the dielectric layer;
partially etching the dielectric layer and the charge-trapping layer using a first mask to remain a portion of the dielectric layer and a portion of the charge-trapping layer on the substrate between the first gate and the second gate and on two opposite sidewalls of the first gate and the second gate to serve for a storage node function; and
implanting a first dopant into the pair of predetermined sourcedrain regions of the active area to form a pair of sourcedrain regions through a second mask covering the middle region of the active area, the first and the second gates and the portion of the charge-trapping layer.
2. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first gate and the second gate are each formed to be entirely on the isolation structure and not to contact the active area.
3. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first gate and the second gate are each formed to be partially on the isolation structure and partially overlap a side portion of the middle region of the active area.
4. The method for manufacturing a non-volatile memory structure according to claim 1, further, before forming the dielectric layer, comprising:
implanting a second dopant into the active area to form a pair of LDD regions through a third mask covering the middle region of the active area.
5. The method for manufacturing a non-volatile memory structure according to claim 4, wherein the third mask comprises a photo resist layer.
6. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the first mask comprises a photo resist layer.
7. The method for manufacturing a non-volatile memory structure according to claim 1, wherein the second mask comprises a photo resist layer.
8. The method for manufacturing a non-volatile memory structure according to claim 1, further comprising implanting a third dopant into the substrate in the active area to form a well.
9. The method for manufacturing a non-volatile memory structure according to claim 1, further comprising forming a contact etch stop layer over the substrate.
10. The method for manufacturing a non-volatile memory structure according to claim 9, further comprising forming two contacts through the contact etch stop layer and on the sourcedrain regions correspondingly.
11. The method for manufacturing a non-volatile memory structure according to claim 1, wherein, the dielectric layer and the charge-trapping layer are etched through the first mask to further remain on other sidewalls of the first gate and the second gate to serve as spacers.
12. A non-volatile memory structure, comprising:
a substrate including an active area and an isolation structure surrounding the active area, wherein the active area comprises a pair of sourcedrain regions and a middle region between the two sourcedrain regions;
a first gate and a second gate disposed entirely on the isolation structure and opposite each other with the middle region of the active area therebetween;
a dielectric layer disposed on the substrate between the first gate and the second gate and on two opposite sidewalls of the first gate and the second gate; and
a charge-trapping layer disposed on the dielectric layer between the first gate and the second gate and between the source region and the drain region and with the dielectric layer together to serve for a storage node function.
13. The non-volatile memory structure according to claim 12, further comprising a pair of LDD regions each between the dielectric layer and each of the sourcedrain regions.
14. The non-volatile memory structure according to claim 12, further comprising:
a contact etch stop layer covering the charge-trapping layer and the sourcedrain regions.
15. The non-volatile memory structure according to claim 14, further comprising:
two contacts disposed through the contact etch stop layer and on the sourcedrain regions correspondingly.
16. The non-volatile memory structure according to claim 12, wherein the active area comprises a well of a dopant.
17. The non-volatile memory structure according to claim 12, wherein the charge-trapping layer is formed as a conformal layer.
18. The non-volatile memory structure according to claim 12, wherein the charge-trapping layer comprises silicon nitride.
19. The non-volatile memory structure according to claim 12, wherein, the dielectric layer and the charge-trapping layer are further disposed on the tops and other sidewalls of the first gate and the second gate to serve as spacers.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. At a computer system including one or more processors and system memory, the computer system also including a physical graphics processing unit (\u201cGPU\u201d), a method for providing a programmable GPU pipeline to a guest application executing in a child partition of a para-virtualized execution environment, the method comprising:
an act of instantiating a virtual machine session, including instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application;
an act of presenting a virtualized graphics processing unit (\u201cvGPU\u201d) to the guest application, the vGPU executing within the child partition, including presenting a plurality of device driver interfaces (\u201cDDIs\u201d) of a rendering framework to the guest application as part of a user-mode driver (\u201cUMD\u201d) of the vGPU, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize one or more features of the rendering framework, including utilizing at least one of: a domain shader, a hull shader, or a geometric shader; and
an act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU for using one or more of a domain shader, a hull shader, or a geometric shader at the physical GPU; and
an act of the render component scheduling the at least one physical GPU-specific command for execution at the physical GPU.
2. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a domain shader.
3. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a hull shader.
4. The method as recited in claim 1, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a geometric shader.
5. The method as recited in claim 1, wherein the UMD converts any graphics commands received from the guest application into corresponding physical GPU-specific commands and stores the corresponding physical GPU-specific commands in a command buffer.
6. The method as recited in claim 5, wherein the act of presenting a vGPU to the guest application comprises an act of presenting a vGPU that includes a kernel-mode driver (\u201cKMD\u201d), the KMD being configured to construct a direct memory access buffer from the command buffer.
7. The method as recited in claim 6, wherein the UMD sends a command buffer containing physical GPU-specific compute shader commands to the KMD.
8. The method as recited in claim 6, wherein instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application comprises an act of negotiating one or more communications protocols among the UMD, the KMD, and the render component, including determining a type of composition device to instantiate based on a version of the rendering framework supported by the UMD.
9. The method as recited in claim 1, wherein the plurality of DDIs enable the guest application to send graphics commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize all features of the rendering framework.
10. The method as recited in claim 9, wherein the rendering framework includes DirectX\xae version 11.
11. The method as recited in claim 9, wherein the UMD comprises a new UMD that is enabled to execute concurrent with a legacy UMD, and wherein the render component is enabled to communicate with both the new UMD and the legacy UMD, such that both a new three-dimensional rendering framework and a legacy three-dimensional rendering can be used concurrently.
12. A computer program product for use at a computer system, the computer program product for implementing a method for providing GPU-accelerated computing functionality to a guest application executing in a child partition of a para-virtualized execution environment, the computer program product comprising one or more computer storage media having stored thereon computer-executable instructions that, when executed at a processor, cause the computer system to perform the method, including the following:
instantiate a virtual machine session, including instantiating a hypervisor that provides (i) a root partition having access to the physical GPU, and (ii) the child partition which executes the guest application;
present a virtualized graphics processing unit (\u201cvGPU\u201d) to the guest application, the vGPU executing within the child partition, including presenting a plurality of device driver interfaces (\u201cDDIs\u201d) of a rendering framework to the guest application as part of a user-mode driver (\u201cUMD\u201d) of the vGPU, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize one or more features of the rendering framework, including utilizing at least one of: a domain shader, a hull shader, or a geometric shader; and
receive, at a render component executing within the root partition, at least one physical GPU-specific command for using one or more of a domain shader, a hull shader, or a geometric shader at the physical GPU; and
schedule the at least one physical GPU-specific command for execution at the physical GPU.
13. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a domain shader.
14. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a hull shader.
15. The computer program product as recited in claim 12, wherein the act of a render component executing within the root partition receiving at least one physical GPU-specific command from the vGPU comprises and act of the render component receiving at least one physical GPU-specific command for using a geometric shader.
16. The computer program product as recited in claim 12, wherein the UMD converts any graphics commands received from the guest application into corresponding physical GPU-specific commands and stores the corresponding physical GPU-specific commands in a command buffer.
17. The computer program product as recited in claim 16, wherein the act of presenting a vGPU to the guest application comprises an act of presenting a vGPU that includes a kernel-mode driver (\u201cKMD\u201d), the KMD being configured to construct a direct memory access buffer from the command buffer.
18. The computer program product as recited in claim 17, wherein the UMD sends a command buffer containing physical GPU-specific compute shader commands to the KMD.
19. The computer program product as recited in claim 12, wherein the plurality of DDIs enable the guest application to send commands to the vGPU for programming a GPU pipeline of the physical GPU to utilize functions of both Direct2D and Direct3D.
20. A computer system, the computer system comprising:
one or more processors;
a graphics processing unit (\u201cGPU\u201d);
system memory; and
one or more computer-readable storage devices having stored thereon computer-executable instructions representing a virtualized graphics processing unit (\u201cvGPU\u201d) and a render component,
wherein the vGPU is configured to execute within the child partition and includes a user-mode driver (\u201cUMD\u201d) configured to:
present a plurality of device driver interfaces (\u201cDDIs\u201d) of a DirectX rendering framework to a guest application executing in a child partition, the plurality of DDIs providing an application programming interface that enables the guest application to send commands to the vGPU for programming a GPU pipeline of the GPU to utilize one or more of: a domain shader, a hull shader, or a geometric shader of the DirectX rendering framework; and
convert vGPU-specific commands to GPU-specific commands; and
wherein the a render component is configured to execute in a root partition and to receive at least one GPU-specific command from the vGPU and to schedule the at least one physical GPU-specific command for execution at the GPU while using one or more of: a domain shader, a hull shader, or a geometric shader of the DirectX rendering framework.