1. An optical amplification device comprising:
a plurality of semiconductor optical amplifiers to which an optical burst signal is input at a different timing;
an optical coupler that combines output signals output from the plurality of semiconductor optical amplifiers;
a detection unit that detects an optical inputting to the plurality of semiconductor optical amplifiers; and
a control unit that activates one of the semiconductor optical amplifiers where the optical inputting is detected, inactivates the other semiconductor optical amplifier, and remains the activation until another optical inputting is detected in the other semiconductor optical amplifier.
2. The optical amplification device as claimed in claim 1, wherein the control unit outputs a signal for informing an alarm when the optical inputting is detected in two or more semiconductor optical amplifiers at a time.
3. The optical amplification device as claimed in claim 1 further comprising a storage unit that stores identification information of two or more semiconductor optical amplifiers where the optical inputting is detected at a time,
wherein when a combination of the semiconductor optical amplifiers stored in the storage unit is changed, the control unit inactivates a common semiconductor optical amplifier stored in the storage unit in the combinations.
4. The optical amplification device as claimed in claim 1, wherein among the plurality of semiconductor optical amplification devices, a deviation among times from a starting time of the detection of the optical inputting by the detection unit to a time when a light regarding the optical inputting reaches the optical coupler is within 512 nsec.
5. An optical amplification method of an optical amplification device combining output signals output by a plurality of semiconductor optical amplifiers to which an optical burst signal is input at a different timing, the method comprising:
activating one of semiconductor optical amplifiers where an optical inputting is detected;
inactivating the other semiconductor optical amplifier; and
remaining the activation until another optical inputting is detected in the other semiconductor optical amplifier.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A data processing apparatus for executing transparent mode access in response to an external request received through a first external bus, said apparatus comprising:
an address conversion circuit including a base address register for setting a start position of an accessible area in a memory space of said data processing apparatus to be accessed by said transparent mode access, said address conversion circuit converting an access destination’s address value supplied through said first external bus, using a value of said base address register; and
a transparency control circuit for executing said transparent mode access to said memory space in said data processing apparatus, using an address value converted by said address conversion circuit.
2. The apparatus according to claim 1, wherein said address conversion circuit further includes an address mask register for setting a range of said accessible area in said memory space of said data processing apparatus, and converts said access destination’s address value using said value of said base address register and a value of said address mask register.
3. The apparatus according to claim 2, wherein said value of said base address register and said value of said address mask register can be changed.
4. The apparatus according to claim 2, wherein transparent mode access to a second external bus different from said first external bus can be executed in response to an external request received through said first external bus.
5. The apparatus according to claim 4, wherein said apparatus further comprises a memory control circuit for controlling a memory connected to said second external bus, and
transparent mode access to said memory can be executed in response to an external request received through said first external bus.
6. The apparatus according to claim 1, wherein said address conversion circuit further includes an addition circuit for adding said value of said base address register to said access destination’s address value.
7. The apparatus according to claim 6, wherein said addition circuit is an OR operation circuit for performing an OR operation of said value of said base address register and said access destination’s address value.
8. A data processing apparatus for executing transparent mode access in response to an external request received through a first external bus, said apparatus comprising:
an address conversion circuit including an address mask register for setting a range of an accessible area in a memory space of said data processing apparatus to be accessed by said transparent mode access, said address conversion circuit converting an access destination’s address value supplied through said first external bus, using a value of said address mask register; and
a transparency control circuit for executing said transparent mode access to said memory space in said data processing apparatus, using an address value converted by said address conversion circuit.
9. The apparatus according to claim 8, wherein said address conversion circuit further includes a mask circuit for masking said access destination’s address value every bit in accordance with said value of said address mask register.
10. The apparatus according to claim 9, wherein said mask circuit is an AND operation circuit for performing an AND operation of said value of said address mask register and said access destination’s address value.
11. The apparatus according to claim 8, wherein said address mask register optionally sets each address signal line, which constitutes an address bus of said first external bus, to be effective or not.
12. A data processing apparatus for executing transparent mode access in response to an external request received through a first external bus, said apparatus comprising:
a base address register for setting a start position of an accessible area in a memory space of said data processing apparatus to be accessed by said transparent mode access;
an address mask register for setting a range of said accessible area in said memory space of said data processing apparatus;
an AND operation circuit for performing an AND operation of an access destination’s address value supplied through said first external bus and a value of said address mask register;
an OR operation circuit for performing an OR operation of an operation result from said AND operation circuit and said value of said base address register; and
a transparency control circuit for executing said transparent mode access to said memory space in said data processing apparatus, using an operation result from said OR operation circuit.
13. The apparatus according to claim 12, wherein said value of said base address register and said value of said address mask register can be changed by said data processing apparatus.
14. The apparatus according to claim 12, wherein said apparatus further comprises a memory control circuit for controlling a memory connected to a second external bus different from said first external bus, and
transparent mode access to said memory can be executed in response to an external request received through said first external bus.
15. A data processing system in which an external bus master is connected through a first external bus with a data processing apparatus capable of executing transparent mode access in response to a request from said external bus master, said data processing apparatus comprising:
an address conversion circuit including a base address register and an address mask register for respectively setting a start position and a range of an accessible area in a memory space of said data processing apparatus to be accessed by said transparent mode access, said address conversion circuit converting an access destination’s address value supplied from said external bus master, using a value of said base address register and a value of said address mask register; and
a transparency control circuit for executing said transparent mode access to said memory space in said data processing apparatus, using an address value converted by said address conversion circuit.
16. The system according to claim 15, wherein said value of said base address register and said value of said address mask register can be changed by said data processing apparatus.
17. The system according to claim 15, wherein said system further comprises a memory connected to said data processing apparatus through a second external bus different from said first external bus, and
said data processing apparatus can execute transparent mode access to said memory in response to a request from said external bus master.
18. An access area control method for controlling an accessible area in a memory space of a data processing apparatus to be accessed by transparent mode access, said method comprising the steps of:
converting a supplied access destination’s address value, using a value of a base address register in which a start position of said accessible area in said memory space of said data processing apparatus has been set; and
executing said transparent mode access to said memory space in said data processing apparatus, using said address value converted.
19. The method according to claim 18, wherein said access destination’s address value is converted using, in addition to said value of said base address register, a value of an address mask register in which a range of said accessible area in said memory space of said data processing apparatus has been set.
20. The method according to claim 19, wherein said value of said base address register and said value of said address mask register can be changed.
21. The method according to claim 18, wherein said access destination’s address value is converted by adding said value of said base address register to said access destination’s address value.
22. An access area control method for controlling an accessible area in a memory space of a data processing apparatus to be accessed by transparent mode access, said method comprising the steps of:
converting a supplied access destination’s address value, using a value of an address mask register in which a range of said accessible area in said memory space of said data processing apparatus has been set; and
executing said transparent mode access to said memory space in said data processing apparatus, using said address value converted.
23. The method according to claim 22, wherein said access destination’s address value is converted by masking said access destination’s address value every bit in accordance with said value of said address mask register.
24. An access area control method for controlling an accessible area in a memory space of a data processing apparatus to be accessed by transparent mode access, said method comprising the steps of:
performing an AND operation of a supplied access destination’s address value and a value of an address mask register in which a range of said accessible area in said memory space of said data processing apparatus has been set;
performing an OR operation of an operation result of said AND operation and a value of a base address register in which a start position of said accessible area in said memory space of said data processing apparatus has been set; and
executing said transparent mode access to said memory space in said data processing apparatus, using an operation result of said OR operation.
25. The method according to claim 24, wherein said value of said base address register and said value of said address mask register can be changed.