What is claimed is:
1. A method, comprising:
acquiring aerial images of a reticle containing a design pattern, wherein the aerial images are acquired for different values of a member of a set of lithographic variables; and
determining a presence of an anomaly in the design pattern by comparing at least one pair of the aerial images corresponding to at least two of the different values.
2. The method of claim 1, wherein one of the different values represents a reference member value.
3. The method of claim 1, wherein the member comprises illumination focus, exposure, degree of partial coherence, illumination mode, or numerical aperture.
4. The method of claim 1, wherein the reticle is a single die reticle or a multi-die reticle.
5. The method of claim 1, wherein the anomaly comprises a design pattern defect.
6. The method of claim 1, wherein the anomaly comprises a reticle enhancement technique defect.
7. The method of claim 1, wherein the anomaly comprises a transient repeating defect that will print under only a portion of the different values.
8. The method of claim 1, wherein the aerial images are acquired with different detectors having the different values.
9. The method of claim 1, further comprising inspecting the reticle for other types of anomalies using one of the aerial images, wherein the other types of anomalies comprise reticle manufacturing errors and contaminants.
10. The method of claim 9, wherein said inspecting comprises a die-to-database comparison or a die-to-die comparison.
11. The method of claim 1, further comprising prior to said determining, preprocessing the at least one pair of the aerial images to remove relatively high intensity values and relatively low intensity values from the at least one pair of the aerial images.
12. The method of claim 1, further comprising identifying regions of the reticle for review based on a location of the anomaly.
13. The method of claim 12, wherein the review comprises aerial image review at varying levels of optical conditions.
14. The method of claim 1, wherein if more than one anomaly is found in the design pattern, the method further comprises binning the more than one anomaly according to regions of the reticle proximate the more than one anomaly.
15. The method of claim 1, further comprising determining a process window for a lithography process to be carried out using the reticle.
16. The method of claim 1, further comprising determining a critical status of the anomaly.
17. A method, comprising:
acquiring aerial images of a reticle containing a design pattern, wherein the aerial images are acquired for different values of a member of a set of lithographic variables;
comparing at least one pair of the aerial images corresponding to at least two of the different values; and
determining an area on the reticle where a lithography process using the reticle is most susceptible to failure based on results of said comparing.
18. The method of claim 17, wherein one of the different values represents a reference member value.
19. The method of claim 18, wherein the area comprises anomalies that are common to the at least one pair of the aerial images not acquired at the reference member value and that are not common to the aerial image acquired at the reference member value.
20. A method, comprising:
inspecting a reticle containing a design pattern for non-transient defects;
acquiring aerial images of the reticle for different values of a member of a set of lithographic variables; and
determining a presence of transient repeating defects on the reticle by subtracting the non-transient defects from the aerial images and comparing at least one pair of the aerial images corresponding to at least two of the different values.
21. The method of claim 20, wherein said inspecting and said acquiring are performed substantially simultaneously.
22. The method of claim 20, wherein said inspecting comprises aerial imaging of the reticle at a reference member value of the set of the lithographic variables.
23. The method of claim 20, wherein said inspecting is performed using a non-aerial imaging reticle inspection system.
24. The method of claim 20, wherein said inspecting comprises a die-to-database comparison or a die-to-die comparison.
25. The method of claim 20, further comprising determining a process window for a lithography process to be carried out using the reticle based on the transient repeating defects.
26. The method of claim 20, wherein the non-transient defects comprise reticle manufacturing errors or contaminants on the reticle.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory comprising:
a plurality of multi-level memory cells, each having a plurality of storable memory states; and
a data converter coupled to the plurality of multi-level memory cells, wherein the data converter is configured to receive a first number of bits of data to be stored in the plurality of multi-level memory cells and convert the first number of bits of data into a second number of bits of data, different than the first number of bits of data, wherein the second number of bits of data specify memory states for each of the plurality of multi-level memory cells.
2. The memory of claim 1 wherein the plurality of multi-level memory cells are configured to store more than two memory states.
3. The memory of claim 1 wherein the data converter is configured to convert the first number of bits of data into two groups of bits of the second number of bits of data.
4. The memory of claim 1, further comprising:
a multiplexer configured to route the second number of bits of data to the plurality of multi-level memory cells.
5. The memory of claim 1 wherein the data converter is configured to convert six or less bits of data into two groups of three or less bits of data.
6. The memory of claim 1 wherein the data converter converts portions of the first number of bits into respective data having second number of bits of data.
7. The memory of claim 1 wherein the data converter is configured to convert the second number of bits of data into the first number of bits of data.
8. A memory comprising:
a plurality of multi-level memory cells, each having a plurality of storable memory states;
a bit mapping circuit configured to map bits of input data to bits of mapped data; and
a data converter circuit coupled to the bit mapping circuit and the plurality of multi-level memory cells, wherein the data converter is configured to convert between the bits of the mapped data and bits of stored data, wherein the stored data is indicative of memory states to be stored by the plurality of multi-level memory cells and the number of bits of the mapped data is different than the number of bits of the stored data.
9. The memory of claim 8, further comprising:
a register coupled to the bit mapping circuit and configured to store the bits of mapped data.
10. The memory of claim 8 wherein the number of bits of input data is a multiple of 2 and the number of bits of the mapped data is not a multiple of 2.
11. The memory of claim 8 wherein pairs of multi-level memory cells are used to store the stored data.
12. The memory of claim 8, further comprising:
a latch coupled to the bit mapping circuit and configured to latch bits of data.
13. The memory of claim 8 wherein the plurality of multi-level memory cells are non-volatile memory cells.
14. The memory of claim 8 wherein the bit mapping circuit is configured to map bits of mapped data to bits of input data.
15. A method, comprising:
receiving a first number of bits of data to be stored in a plurality of multi-level memory cells, the multi-level memory cells configured to store more than two memory states; and
converting the first number of bits of data into a second number of bits of data, wherein the second number is different than the first number and the second number of bits of data specify memory states for each of the plurality of multi-level memory cells.
16. The method of claim 15, further comprising:
reading memory states of the plurality of multi-level memory cells to determine the second number of bits of data;
converting the second number of bits of data into the first number of bits of data; and
providing the first number of bits of data.
17. The method of claim 15, further comprising:
storing the first number of bits of data in a register before converting the first number of bits of data into a second number of bits of data.
18. The method of claim 15, further comprising:
storing the memory states in the plurality of multi-level memory cells.
19. A method comprising:
mapping original data to intermediate data; and
storing the intermediate data in multi-level memory cells, wherein the intermediate data is based at least in part on the original data and the intermediate data is stored as memory states in the multi-level memory cells, and wherein the intermediate data has a different number of bits than the original data from which the intermediate data is at least in part based.
20. The method of claim 19 wherein mapping original data to intermediate data comprises:
dividing the original data into a plurality of N-bit binary data; and
converting the plurality of N-bit binary data into respective M-bit intermediate data, wherein M is not equal to N.
21. The method of claim 19 wherein the intermediate data in multi-level memory cells comprises storing the intermediate data as memory states in a plurality of multi-level cells.