1-26. (canceled)
27. A single chip microcontroller unit, comprising:
a processing unit having normal power mode of operation and a low power mode of operation;
analog circuitry connected to the processing unit;
digital circuitry connected to the processing unit;
a power management unit controlling power operation of the processing unit, the analog circuitry and the digital circuitry; and
a system voltage monitoring circuit for generating a system voltage control signal to maintain the power management unit in a reset mode responsive to a system voltage level with respect to a predetermined level during start-up of the single chip microcontroller unit.
28. The single chip microcontroller unit of claim 27, wherein the system voltage monitoring circuit further comprises:
an uncalibrated system voltage detector for generating a first control signal responsive to the system voltage level with respect to the predetermined level;
power on reset circuitry for generating a power on reset signal to maintain the power management unit in the reset state when the first control signal indicates the system voltage level does not exceed the predetermined level;
a calibrated system voltage detector for generating a second control signal responsive to the system voltage level with respect to the predetermined level;
control logic connected to receive the first control signal, the reset signal and the second control signal for generating an indication whether the system voltage level exceeds the predetermined level responsive to the first control signal, the reset signal and the second control signal.
29. The single chip microcontroller unit of claim 28, wherein the calibrated system voltage detector has the predetermined level calibrated responsive to a plurality of trim bits from the processing unit.
30. The single chip microcontroller unit of claim 28, wherein the control logic further comprises:
a NOR gate connected to receive the second control signal from the calibrated system voltage detector at a first input of the NOR gate and the reset signal on a second input of the NOR gate; and
an AND gate having a first input of the AND gate connected to an output of the NOR gate and a second input of the AND gate connected to receive the first control signal from the uncalibrated system voltage detector, the AND gate generating the indication of whether the system voltage lever exceeds the predetermined level on an output of the AND gate.
31. A single chip microcontroller unit, comprising:
a processing unit having normal power mode of operation and a low power mode of operation;
analog circuitry connected to the processing unit;
digital circuitry connected to the processing unit;
a power management unit controlling power operation of the processing unit, the analog circuitry and the digital circuitry; and
a system voltage monitoring circuit for generating a system voltage control signal to the power management unit responsive to a system voltage level with respect to a predetermined level, wherein the system voltage monitoring circuit further comprises:
an uncalibrated system voltage detector for generating a first control signal responsive to the system voltage level with respect to the predetermined level;
power on reset circuitry for generating a power on reset signal to maintain the single chip microcontroller unit in a reset state when the first control signal indicates the system voltage level does not exceed the predetermined level;
a calibrated system voltage detector for generating a second control signal responsive to the system voltage level with respect to the predetermined level; and
control logic connected to receive the first control signal, the reset signal and the second control signal for generating an indication whether the system voltage level exceeds the predetermined level responsive to the first control signal, the reset signal and the second control signal.
32. The single chip microcontroller unit of claim 31, wherein the calibrated system voltage detector has the predetermined level calibrated responsive to a plurality of trim bits from the processing unit.
33. The single chip microcontroller unit of claim 31, wherein the control logic further comprises:
a NOR gate connected to receive the second control signal from the calibrated system voltage detector at a first input of the NOR gate and the reset signal on a second input of the NOR gate; and
an AND gate having a first input of the AND gate connected to an output of the NOR gate and a second input of the AND gate connected to receive the first control signal from the uncalibrated system voltage detector, the AND gate generating the indication of whether the system voltage lever exceeds the predetermined level on an output of the AND gate.
34. A method for monitoring a system voltage during start-up, comprising the steps of:
powering up a single chip microcontroller unit;
performing an uncalibrated measurement of the system voltage level with respect to a predetermined level;
generating a first control signal responsive to the calibrated measurement;
generating a power on reset signal to maintain the single chip microcontroller unit in a reset state when the first control signal indicates the system voltage level does not exceed the predetermined level;
performing a calibrated measurement responsive to the system voltage level with respect to the predetermined level;
generating a second control signal responsive to the calibrated measurement; and
generating an indication whether the system voltage level exceeds the predetermined level responsive to the first control signal, the reset signal and the second control signal.
35. The method of claim 34, wherein the step of performing the calibrated measurement further comprises the step of calibrating a system voltage detector responsive to a plurality of trim bits from a control unit.
36. A single chip microcontroller unit, comprising:
a processing unit having normal power mode of operation and a low power mode of operation;
analog circuitry connected to the processing unit;
digital circuitry connected to the processing unit;
a power management unit controlling power operation of the processing unit, the analog circuitry and the digital circuitry; and
a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level.
37. The single chip microcontroller unit of claim 36, wherein the supply monitoring circuit further comprises:
a first comparator circuit for comparing a band gap voltage to a reference threshold voltage; and
an enable circuit for disabling the first comparator circuit until the band gap voltage stabilizes at start up.
38. The single chip microcontroller unit of claim 37, wherein the supply monitoring circuit further comprises a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit.
39. The single chip microcontroller unit of claim 37, wherein the enable circuit further comprises:
a voltage supply detector for determining when the supply voltage exceeds a voltage supply threshold and generating a first indication responsive thereto;
a band gap voltage detector for determining when the band gap voltage exceeds band gap voltage threshold and generating a second indication responsive thereto; and
control logic for an enable signal responsive to the first indication and the second indication.
40. The single chip microcontroller of claim 37, further wherein the reference threshold voltage is adjustable responsive to a plurality of bits provided by the control processor.
41. The single chip microcontroller of claim 37, wherein the supply monitoring circuit further comprises:
a second supply monitoring circuit for generating an indication when the supply voltage exceeds a higher threshold level; and
wherein the enable circuit further disables the second supply monitoring circuit until the band gap voltage stabilizes at start up.
42. The single chip microcontroller unit of claim 41, wherein the second supply monitoring circuit further comprises a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit.
43. A single chip microcontroller unit, comprising:
a processing unit having normal power mode of operation and a low power mode of operation;
analog circuitry connected to the processing unit;
digital circuitry connected to the processing unit;
a power management unit controlling power operation of the processing unit, the analog circuitry and the digital circuitry; and
a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level and generating a power control signal to the power management unit responsive thereto, wherein the supply monitoring circuit further comprises:
a first comparator circuit for comparing a band gap voltage to a reference threshold voltage; and
an enable circuit for disabling the first comparator circuit until the band gap voltage stabilizes at start up.
a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit.
44. The single chip microcontroller unit of claim 43, wherein the enable circuit further comprises:
a voltage supply detector for determining when the supply voltage exceeds a voltage supply threshold and generating a first indication responsive thereto;
a band gap voltage detector for determining when the band gap voltage exceeds band gap voltage threshold and generating a second indication responsive thereto; and
control logic for an enable signal responsive to the first indication and the second indication.
45. The single chip microcontroller of claim 43, further wherein the reference threshold voltage is adjustable responsive to a plurality of bits provided by the control processor.
46. The single chip microcontroller of claim 43, wherein the supply monitoring circuit further comprises:
a second supply monitoring circuit for generating an indication when the supply voltage exceeds a higher threshold level; and
wherein the enable circuit further disables the second supply monitoring circuit until the band gap voltage stabilizes at start up.
47. The single chip microcontroller unit of claim 46, wherein the second supply monitoring circuit further comprises a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit.
48. A single chip microcontroller unit, comprising:
a processing unit having normal power mode of operation and a low power mode of operation;
analog circuitry connected to the processing unit;
digital circuitry connected to the processing unit;
a power management unit controlling power operation of the processing unit, the analog circuitry and the digital circuitry; and
a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level and generating a power control signal to the power management unit responsive thereto, wherein the supply monitoring circuit further comprises:
a first comparator circuit for comparing a band gap voltage to a reference threshold voltage; and
an enable circuit for disabling the first comparator circuit until the band gap voltage stabilizes at start up;
a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit;
a second supply monitoring circuit for generating an indication when the supply voltage exceeds a higher threshold level; and
wherein the enable circuit further disables the second supply monitoring circuit until the band gap voltage stabilizes at start up.
49. The single chip microcontroller unit of claim 48, wherein the enable circuit further comprises:
a voltage supply detector for determining when the supply voltage exceeds a voltage supply threshold and generating a first indication responsive thereto;
a band gap voltage detector for determining when the band gap voltage exceeds band gap voltage threshold and generating a second indication responsive thereto; and
control logic for an enable signal responsive to the first indication and the second indication.
50. The single chip microcontroller of claim 48, further wherein the reference threshold voltage is adjustable responsive to a plurality of bits provided by the control processor.
51. The single chip microcontroller of claim 48, wherein the supply monitoring circuit further comprises:
a second supply monitoring circuit for generating an indication when the supply voltage exceeds a higher threshold level; and
wherein the enable circuit further disables the second supply monitoring circuit until the band gap voltage stabilizes at start up.
52. The single chip microcontroller unit of claim 51, wherein the second supply monitoring circuit further comprises a disable circuit for disabling the supply monitoring circuit responsive to a disable control signal from the processing unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for performing an implicit predicted return from a predicted subroutine in a processor, the system comprising:
a branch history tablebranch target buffer (BHTBTB) to hold branch information, wherein the branch information includes a target address of a predicted subroutine and a branch type;
instruction buffers to buffer fetched instructions; and
instruction fetch controls (IFC) for performing a method comprising:
fetching a branch instruction at a branch address and a return-point instruction at an address subsequent to the branch address;
receiving the target address of the predicted subroutine and the branch type associated with the branch address via the BHTBTB;
fetching a fixed number of instructions starting at the target address of the predicted subroutine in response to the branch type indicating that the predicted subroutine is a fixed-length subroutine; and
referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction: and
wherein the fixed-length subroutine is associated with only a single row in the BHTBTB.
2. The system of claim 1 wherein the branch information further comprises a length field that specifies the fixed number of instructions as a number of instructions or as a number of bytes.
3. The system of claim 1 wherein the branch type defines the fixed number of instructions.
4. The system of claim 1 wherein the instruction buffers to send the fixed number of instructions to an instruction decode unit (IDU) between the instructions at the branch address and at the address subsequent to the branch address.
5. The system of claim 1 wherein the IFC provides buffer controls to the instruction buffers.
6. The system of claim 1 wherein a standard subroutine is associated with at least two rows in the BHTBTB.
7. The system of claim 1 wherein the BHTBTB is searched relative to the branch address to locate the target address of the predicted subroutine and the branch type.
8. A method for performing an implicit predicted return from a predicted subroutine in a processor, the method comprising:
fetching a branch instruction at a branch address and a return-point instruction at an address subsequent to the branch address;
searching a branch history tablebranch target buffer (BHTBTB) to locate the branch address, wherein the BHTBTB holds branch information including a target address of a predicted subroutine and a branch type;
fetching a fixed number of instructions starting at the target address of the predicted subroutine in response to the branch type indicating that the predicted subroutine is a fixed-length subroutine; and
referencing the return-point instruction such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction; and
wherein the fixed-length subroutine is associated with only a single row in the BHTBTB.
9. The method of claim 8 wherein the branch information further comprises a length field that specifies the fixed number of instructions as a number of instructions or as a number of bytes.
10. The method of claim 8 wherein the branch type defines the fixed number of instructions.
11. The method of claim 8 further comprising:
sending the fixed number of instructions to an instruction decode unit (IDU) between the instructions at the branch address and at the address subsequent to the branch address.
12. The method of claim 8 wherein a standard subroutine is associated with at least two rows in the BHTBTB.
13. The method of claim 8 wherein the fetching is performed by instruction fetch controls (IFC) and the instructions are buffered in instruction buffers.
14. A computer program product for performing an implicit predicted return from a predicted subroutine in a processor, the computer program product comprising:
a computer-readable storage medium for storing instructions including an implicit predicted return from a predicted subroutine, comprising a method of:
calling a fixed-length subroutine via a branch instruction at a branch address, wherein the fixed-length subroutine is predictively fetched as a predicted subroutine; and
returning to an address subsequent to the branch address absent a return branch instruction in the predicted subroutine upon predictively fetching a fixed number of instructions in the predicted subroutine; and
wherein the fixed-length subroutine is associated with only a single row in the BHTBTB.
15. The computer program product of claim 14 wherein predictively fetching the fixed number of instructions further comprises:
searching a branch history tablebranch target buffer (BHTBTB) to locate the branch address, wherein the BHTBTB holds branch information including a target address of the predicted subroutine and a branch type; and
fetching the fixed number of instructions starting at the target address of the predicted subroutine in response to the branch type indicating that the predicted subroutine is of a fixed-length.
16. The computer program product of claim 15 wherein the branch information further comprises a length field that specifies the fixed number of instructions as a number of instructions or as a number of bytes.
17. The computer program product of claim 15 wherein the branch type defines the fixed number of instructions.
18. The computer program product of claim 15 wherein a standard subroutine is associated with at least two rows in the BHTBTB.
19. The computer program product of claim 15 wherein the fetching is performed by instruction fetch controls (IFC) and the instructions are buffered in instruction buffers.
20. The computer program product of claim 14 wherein the fixed number of instructions are sent to an instruction decode unit (IDU) between the instructions at the branch address and at the address subsequent to the branch address.