1. An inventory sensor comprising:
a plurality of first conductive elements, each disposed in a first layer and connected to an electrical supply line;
a plurality of second conductive elements, each disposed in a second layer and aligned such that each second conductive element opposes one of the plurality of first conductive elements, each second conductive element connected to a unique electrical return line;
wherein each of said plurality of first conductive elements are adapted to move into contact with the respective opposing second conductive element when force is applied to said first conductive element in the direction of second conductive element; and
wherein said electrical supply line and said unique electrical return line for each of said plurality of second conductive elements are connected to a controller which monitors each unique electrical return line to determine a footprint associated with a retail item placed on said inventory sensor, and wherein said controller compares the determined footprint to a database of stored retail item footprints to identify the retail item placed on said inventory sensor.
2. The inventory sensor of claim 1 wherein said controller monitors each unique electrical return line to determine a quantity of footprints associated with the retail items placed on said inventory sensor.
3. The inventory sensor of claim 1 wherein said controller additionally determines the weight of the retail items placed on said inventory sensor.
4. The inventory sensor of claim 3 wherein said controller compares the determined retail item weight to a database of stored retail item weights to determine a quantity of retail items placed on said inventory sensor.
5. The inventory sensor of claim 4 wherein said controller performs a lookup in said database for the identified retail items to determine a predetermined low inventory threshold associated with said retail item and generates a warning when the determined quantity falls below the predetermined low inventory threshold.
6. The inventory sensor of claim 5 wherein said controller monitors each unique electrical return line to determine a quantity of footprints associated with the retail items placed on said inventory sensor and wherein said quantity of footprints, said determined retail item weight, and said determined quantity of retail items are cross-referenced to identify an out of place retail item condition.
7. The inventory sensor of claim 6 wherein a visual indication is generated at the inventory sensor or at an associated display when a retail item having a non-matching footprint or non-matching weight is detected at the controller on the inventory sensor.
8. The inventory sensor of claim 1 further comprising a third layer disposed between said first layer and said second layer to provide biasing such that each of said plurality of first conductive elements and each of said plurality of second conductive elements are not in contact when force is not applied to said first conductive element in the direction of second conductive element.
9. An inventory sensor comprising:
a plurality of opposing contact pairs, each opposing contact pair comprising a first contact disposed in a first layer and a second contact disposed in a second layer, wherein each opposing contact pair is biased such that said first contact and said second contact are not connected, said biasing provided by a third layer disposed between said first layer and said second layer;
wherein each of the plurality of first contacts is electrically connected to one of a plurality of supply lines and each of the plurality of second contacts is electrically connected to one of a plurality of return lines;
wherein each of said first contacts, said second contacts, said supply lines and said return lines are formed from conductive material, such that bringing one of said first contact and one of said second contact into connection forms a conductive path comprising the supply line, the first contact, the second contact, and the return line;
wherein said first layer, said second layer, and said third layer collectively form a mat having a forward edge facing a front edge of a shelf, with said plurality of opposing contact pairs arranged into a plurality regions in said mat, said plurality of regions arranged transverse to a forward-aft axis of said mat; and
wherein each of the plurality of supply lines and each of the plurality of return lines are connected to a processor for determining a footprint associated with a retail item placed on said mat.
10. The inventory sensor of claim 9 wherein the processor determines in which region of said plurality of regions said retail item is located.
11. The inventory sensor of claim 9 wherein said processor determines a quantity of footprints associated with the retail items placed on said mat.
12. The inventory sensor of claim 9 wherein said processor compares the determined footprint to a database of stored retail item footprints to identify the retail item placed on said mat.
13. The inventory sensor of claim 11 wherein said processor transmits the determined quantity of retail item footprints to a display associated with said mat.
14. The inventory sensor of claim 9 wherein each of said plurality of second contacts is electrically connected to one of a plurality of return lines which is unique to that second contact.
15. The inventory sensor of claim 9 wherein said third layer comprises a granulated material adapted to permit air flow between opposing contacts of opposing contact pairs.
16. The inventory sensor of claim 11 wherein said processor is disposed within an electronic shelf label electrically connected to said mat.
17. The inventory sensor of claim 9 wherein the bringing one of said first contact and one of said second contact into connection to form a conductive path is caused by placing a retail item on said mat.
18. The inventory sensor of claim 11 wherein said processor generates a warning for store personnel when the determined quantity of retail item footprints falls below a predetermined threshold.
19. The inventory sensor of claim 11 wherein said processor generates an alarm for store personnel when the determined quantity of retail item footprints is zero.
20. The inventory sensor of claim 11 wherein said processor is disposed with said mat, and wherein said processor is inductively coupled to an inventory control system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multichip module comprising at least one first semiconductor chip and at least one second semiconductor chip, the semiconductor chips being arranged in a coplanar manner with respect to each other on or in a support medium and including contact areas arranged on active top sides of the first and second semiconductor chips;
wherein at least one second semiconductor chip is arranged adjacent with at least one first semiconductor chip, and the at least one second semiconductor chip includes an arrangement of contact areas that is at least partly mirror image symmetrical in relation to an arrangement of contact areas of the at least one first semiconductor chip that is adjacent the second semiconductor chip such that contact areas disposed at or near a first edge of a first semiconductor chip are aligned and correspond with contact areas disposed at or near a first edge of an adjacent second semiconductor chip that faces the first edge of the first semiconductor chip, and contact areas disposed at or near a second edge of the first semiconductor chip that opposes the first edge of the first semiconductor chip are aligned and correspond with contact areas disposed at or near a second edge of the adjacent second semiconductor chip that opposes the first edge of the second semiconductor chip; and
wherein first wiring arrangements extend between contact areas of adjacent first and second semiconductor chips, and second wiring arrangements extend from contact areas on at least some of the semiconductor chips to external contacts on the multichip module.
2. The multichip module of claim 1, wherein a respective first semiconductor chip is associated with a single second semiconductor chip such that an arrangement of contact areas of the single second semiconductor chip is mirror image symmetrical in relation to the contact areas of the respective first semiconductor chip.
3. The multichip module of claim 1, further comprising a plurality of first semiconductor chips and a plurality of second semiconductor chips, wherein the first semiconductor chips and the second semiconductor chips are arranged in a checkerboard-like pattern such that each first semiconductor chip is adjacent at least one second semiconductor chip and each second semiconductor chip is adjacent at least one first semiconductor chip.
4. The multichip module of claim 1, wherein the at least one second semiconductor chip includes an arrangement of components that is at least partly mirror image symmetrical in relation to an arrangement of components of the at least one first semiconductor chip such that components disposed at or near the first edge of the first semiconductor chip are aligned and conespond with a same type of components disposed at or near the first edge of the adjacent second semiconductor chip that faces the first edge of the first semiconductor chip, and components disposed at or near the second edge of the first semiconductor chip that opposes the first edge of the first semiconductor chip are aligned and correspond with a same type of components disposed at or near the second edge of the adjacent second semiconductor chip that opposes the first edge of the second semiconductor chip.
5. The multichip module of claim 1, further comprising wiring lines that connect contact areas disposed on a first semiconductor chip with contact areas disposed on an adjacent second semiconductor chip, wherein the wiring lines connect contact areas between the first and second semiconductor chips that are arranged at mirror image symmetrical locations with respect to each other and in relation to the first edges of the first and second semiconductor chips.
6. The multichip module of claim 1, wherein the support medium comprises a circuit substrate including a first side with contact pads that are connected, via through contacts, to external contacts arranged on a second side of the circuit substrate, passive reverse sides of the semiconductor chips are disposed on the first side of the circuit substrate, the first wiring arrangements include first bonding connections and portions of the second wiring arrangements include second bonding connections, the second bonding connections connect contact areas to the contact pads, and the semiconductor chips and the first and second bonding are encased in a plastic compound.
7. The multichip module of claim 1, wherein the support medium comprises a primary board including a first side that faces the active top sides of the semiconductor chips and holds metal wiring arrangements in at least one rewiring layer, the metal wiring arrangements being connected, via through contacts, to external contacts arranged on a second side of the primary board, the contact areas of the semiconductor chips are connected via flip chip contacts to the metal wiring arrangements, and a plastic compound encases the semiconductor chips and the first side of the primary board including the metal wiring arrangements and the flip chip contacts.
8. The multichip module of claim 1, wherein the support medium comprises a plastic compound that encloses the semiconductor chips such that the active top sides of the semiconductor chips remain uncovered, a patterned insulating layer comprising one of polyimide and benzocyclobutene extends over the active top sides of the semiconductor chips and over regions of a top side of the plastic compound that are arranged between and adjacent the semiconductor chips such that the contact areas of the semiconductor chips remain uncovered, the first rewiring arrangements are arranged at least partially on the patterned insulating layer such that each first rewiring arrangement connects together opposite contact areas from semiconductor chips that are situated adjacent each other, and the second rewiring arrangements are arranged at least partially on the patterned insulating layer to connect contact areas disposed at outer edges of the semiconductor chips to external contacts arranged on the insulating layer.
9. The multichip module of claim 1, wherein the support medium comprises a circuit carrier comprising metal, the circuit carrier including a top side onto which a passive reverse side of each of the semiconductor chips connects via an adhesive layer, the first wiring arrangements and the second wiring arrangements are situated in at least one patterned rewiring layer that includes external contact areas on which the external contacts are arranged, and the at least one patterned rewiring layer extends over the active top sides of the semiconductor chips and over the top side of the circuit carrier.
10. The multichip module of claim 9, wherein a patterned insulating layer extends below the first wiring arrangements and the second wiring arrangements and at least over regions of the top side of the circuit carrier that are not covered by the semiconductor chips.
11. The multichip module of claim 10, wherein the layer thickness of the insulating layer correspond with at least one of the height of the semiconductor chips and the combined height of the semiconductor chips and the adhesive layer.
12. The multichip module of claim 10, wherein the patterned insulating layer and regions of the active top sides of the semiconductor chips support a further patterned insulating layer on which the first wiring arrangements and the second wiring arrangements are routed.
13. The multichip module of claim 12, wherein the combined layer thickness of the patterned insulating layer and the further patterned insulating layer is at least the same dimension as the height of the semiconductor chips and the layer thickness of the adhesive layer.
14. The multichip module of claim 10, wherein transitional points comprising an elastomer material are adjacent to the semiconductor chips, the transitional points support the first wiring arrangements and the second wiring arrangements and are used to route the first wiring arrangements and the second wiring arrangements from the active top sides of the semiconductor chips to the top side of the circuit carrier or to the patterned insulating layer.
15. A printed circuit board comprising at least one first component arranged thereon and at least one second component arranged thereon, the components comprising one of ball grid arrays and flat conductor frame based packages and including contact pads;
wherein at least one second component is arranged adjacent with at least one first component, and the at least one second component includes an arrangement of contact areas that is at least partly mirror image symmetrical in relation to an arrangement of contact areas of the at least one first component that is adjacent the at least one second component such that contact areas contact areas disposed at or near a first edge of a first component are aligned and correspond with contact areas disposed at or near a first edge of an adjacent second component that faces the first edge of the first component, and contact areas disposed at or near a second edge of the first component that opposes the first edge of the first component are aligned and correspond with contact areas disposed at or near a second edge of the adjacent second component that opposes the first edge of the second component; and
wherein first wiring arrangements extend between contact areas of adjacent first and second components, and second wiring arrangements extend from contact areas on at least some of the components to external contacts on the multichip module.
16. An electronic device comprising:
at least one thin-ground semiconductor chip including a height of less than 150 \u03bcm and contact areas and further including a passivation layer on an active top side of the semiconductor chip;
at least one circuit carrier comprising a metal or an alloy, wherein a passive reverse side of the at least one thin-ground semiconductor chip is secured onto a top side of the circuit carrier with an adhesive layer;
a photopatterned insulating layer formed of one of cardo, benzocyclobutene and polyimide, and extending next to the at least one thin-ground semiconductor chip and over the top side of the circuit carrier so as to leave exposed a saw channel at the edge of the electronic device, wherein the layer thickness of the photopatterned insulating layer corresponds with the sum of the height of the at least one thin-ground semiconductor chip and the layer thickness of the adhesive layer arranged below the at least one thin-ground semiconductor chip, and wherein trenches are arranged between lateral faces of the at least one thin-ground semiconductor chip and the photopatterned insulating layer and the trenches are filled with an insulating material;
line paths disposed on at least one rewiring layer and that are routed on at least one of the photopatterned insulating layer, the insulating material of the trenches, the passivation layer of the active top side of the at least one thin-ground semiconductor chip and the circuit carrier in the saw channel, wherein the line paths connect at least two of the contact areas of the at least one thin-ground semiconductor chip, external contact areas arranged on the photopatterned insulating layer and the circuit carrier; and
external contacts arranged on the external contact areas.
17. The electronic device of claim 16, wherein the circuit carrier comprises an ironchromiumnickel alloy.
18. The electronic device of claim 16, wherein the circuit carrier has a coefficient of thermal expansion between 11.3 16.6 ppm\xb0K and 16.6 ppm\xb0K.
19. The electronic device of claim 16, wherein the insulating material of the trenches comprises the same material that forms the insulating adhesive layer disposed below the at least one thin-ground semiconductor chip.
20. The electronic device of claim 16, wherein the insulating material of the trenches comprises one of benzocyclobutene, polyimide and cardo.
21. The electronic device of claim 16, wherein the circuit carrier is placed at a defined potential via line paths extending to the edge of the electronic device.
22. A method for fabricating electronic devices comprising:
forming a rectangular circuit carrier from metal or an alloy and including a support top side;
providing at least one semiconductor chip including contact areas and a passivation layer on an active top side of the at least one semiconductor chip, wherein the at least one semiconductor chip is thin-ground to a height of less than 150 \u03bcm;
securing an insulating layer formed of one of cardo, benzocyclobutene and polyimide onto a surface of the circuit carrier such that a layer thickness of the insulating layer corresponds to the total sum of the heights of the at least one thin-ground semiconductor chip and a layer thickness of an adhesive layer that is to be arranged below the at least one semiconductor chip;
photopatterning the insulating layer such that at least one free region is produced on the circuit carrier for receiving the at least one thin-ground semiconductor chip;
securing the at least one thin-ground semiconductor chip, with a passive reverse side of the at least one thin-ground semiconductor chip, into the at least one free region on the circuit carrier using an adhesive layer;
filling trenches defined between lateral faces of the at least one thin-ground semiconductor chip and the photopatterned insulating layer with an insulating material;
forming line paths with at least one rewiring layer on at least one of the photopatterned insulating layer, the insulating material of the trenches, the passivation layer on the active top side of the at least one thin-ground semiconductor chip and external contact areas disposed on the photopatterned insulating layer, wherein the line paths make at least partial contact with the contact areas of the at least one thin-ground semiconductor chip;
putting external contacts onto the external contact areas; and splitting the circuit carrier at outer edges of the circuit carrier into individual electronic devices.
23. The method of claim 22, wherein the trenches between the lateral faces of the at least one thin-ground semiconductor chip and the photopatterned insulating layer are filled by putting on and photopatterning a further insulating layer formed of one of benzocyclobutene, polyimide and cardo.
24. The method of claim 22, wherein the trenches between the lateral faces of the at least one thin-ground semiconductor chip and the photopatterned insulating layer are filled by adhesive when the at least one thin-ground semiconductor chip is put onto the circuit carrier, wherein the quantity of adhesive for each thin-ground semiconductor chip is proportioned such that the sum of the volume of the quantity of adhesive and the volume of the respective thin-ground semiconductor chip correspond at least to the volume of a respective free region of the photopatterned insulating layer.