1. A computer-implemented method comprising:
defining a debugging script;
defining at least one trigger point and associating the at least one trigger point with the debugging script;
compiling the debugging script on the fly;
identifying a defined trigger point in a section of code during run time of a debuggee; and
executing the debugger script in response to the identification of the defined trigger to automatically debug the code.
2. A method as in claim 1, wherein the defining a debugging script comprises: generating a new debugging script.
3. A method as in claim 1, wherein the defining a debugging script comprises: modifying a pre-defined debugging script.
4. A method as in claim 3, wherein the modifying a pre-defined debugging script comprises: launching a stand-alone editor; populating the stand-alone editor with the pre-defined debugging script; and receiving user-generated input to modify the pre-defined debugging script.
5. A method as in claim 3, wherein the modifying a pre-defined debugging script comprises: accessing an integrated editor during debugging; populating the integrated editor with the pre-defined debugging script; and receiving user-generated input to modify the pre-defined debugging script.
6. A method as in claim 1, further comprising: saving the defined debugging script to a script repository.
7. A method as in claim 1, wherein the defining a trigger point comprises: creating a new trigger point.
8. A method as in claim 1, wherein the defining a debugging script comprises: modifying a pre-defined trigger point.
9. A method as in claim 8, wherein the modifying a pre-defined trigger point comprises: launching a stand-alone editor; populating the stand-alone editor with the pre-defined trigger point; and receiving user-generated input to modify the pre-defined trigger point.
10. A method as in claim 8, wherein the modifying a pre-defined trigger point comprises: accessing an integrated editor during debugging; populating the stand-alone editor with the pre-defined trigger point; and receiving user-generated input to modify the pre-defined trigger point.
11. A method as in claim 1, wherein the defining a trigger point comprises: associating a trigger point with a debugger script or an existing combination of a debugger script with a pre-defined trigger point.
12. A method as in claim 1, wherein the code is in Advanced Business Application Programming language.
13. A method as in claim 1, wherein the debugger script is in Advanced Business Application Programming language.
14. A method as in claim 1, wherein the trigger point is based on a user-defined watchpoint.
15. A method as in claim 1, wherein the trigger point is based on a user-defined breakpoint.
16. A method as in claim 1, wherein the trigger point is the current position of the code of the debuggee.
17. A method as in claim 16, wherein reaching the trigger point causes an immediate execution of the debugging script.
18. A method as in claim 1, wherein the code contains a trigger point after each step traversed by a debugger.
19. A computer-implemented method comprising:
defining one or more trigger points in a section of code to be debugged;
associating the trigger points with a debugger script or with a combination of debugger script and additional trigger points;
creating a debugger and executing the debugger script in response to identifying the defined trigger points during run time of a debuggee to automatically debug the code.
20. A computer-implemented method comprising:
identifying a trigger point within a section of code to be debugged;
launching a debugger script editor;
compile a debugger script generated on the fly in the script editor; and
executing the compiled debugger script to debug the code.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor power device comprising:
a source region of a first conductivity type;
a body region of a second conductivity type encompassing said source region;
a first drain region of said first conductivity type disposed outside of edge termination;
a gate separated by an insulating layer from channel region of said body region;
a source metal layer connected to said source regions and said body regions;
a first gate metal connected to said gate;
a first drain metal connected to said first drain region;
said source region, said body region, said gate and said first drain region formed in a top side of semiconductor chip;
a gate-drain clamp diode connected between a second gate metal on the gate-drain clamp diode and said first drain metal, composed of multiple back-to-back polysilicon Zener diodes disposed outside of edge termination area without having said polysilicon Zener diode or said second gate metal cross over said edge termination;
a second drain region formed on a bottom side of said semiconductor chip;
a second drain metal layer connected to said second drain region; and
said first and second gate metals connected together at a gate lead frame through at least one bonding wire.
2. The semiconductor power device of claim 1, wherein said first gate metal and second gate metal connect together to said gate lead frame through two separated bond wires.
3. The semiconductor power device of claim 1, wherein said second gate metal connects to said first gate metal and then said gate lead frame through a single bond wire.
4. The semiconductor power device of claim 1 is a trench MOSFET comprising a plurality of semiconductor power cells in active area with each cell comprising said gate which is a trenched gate surrounded by said source region encompassed in said body region above said second drain region;
said second drain region of said first conductivity type disposed on a bottom surface of a low-resistivity substrate with said first type conductivity, and
said trench MOSFET cell further comprises an epitaxial layer of said first conductivity type over said substrate, said epitaxial layer having a lower doping concentration than said substrate.
5. The semiconductor power device of claim 4 further comprises an on-resistance reduction implantation region having same conductivity type as said source region surrounding trench bottom of each said trenched gate, with doping concentration higher than said epitaxial layer.
6. The semiconductor power device of claim 1 is a trench IGBT wherein:
said gate is a trenched gate;
said source region is an emitter region of said first conductivity type;
said body region is a base region of said second conductivity type;
said first drain region is a first collector region of said first conductivity type;
said source metal is a emitter metal;
said first drain metal is a first collector metal; and
said gate-drain clamp diode is a gate-collector clamp diode.
7. The semiconductor power device of claim 6 further comprises an on-resistance reduction implantation region having same conductivity type as said emitter region surrounding trench bottom of each said trenched gate.
8. The semiconductor power device of claim 6 is a PT trench IGBT further comprising:
a heavily doped substrate of said second conductivity type;
a first epitaxial layer of said first conductivity type grown on said substrate;
a second epitaxial layer of said first conductivity type grown on said first epitaxial layer, having less doping concentration than said first epitaxial layer; and
a second collector region of said second conductivity type is disposed on said bottom side of said substrate.
9. The semiconductor power device of claim 6 is a NPT trench IGBT further comprising:
a lightly doped substrate of said first conductivity type; and
a second collector region of said second conductivity type is disposed on the bottom side of said lightly doped substrate.
10. The semiconductor power device of claim 6 is a NPT trench IGBT further comprising:
a lightly doped substrate of said first conductivity type; and
a second collector region comprising alternately heavily doped regions with said first and second type conductivity formed on the bottom side of said lightly doped substrate.