What is claimed is:
1. A method for the selection of optical signal quality for the transmission of data, comprising the steps of:
(a) receiving an incoming optical signal;
(b) splitting the incoming optical signal into a first split signal and a second split signal;
(c) evaluating the quality of the first split signal in a first optical performance monitor;
(d) generating and transmitting from the first optical performance monitor to a signal selector engine a first electrical message indicative of the quality of the first split signal;
(e) evaluating the quality of the second split signal in a second optical performance monitor;
(f) generating and transmitting from the second optical performance monitor to the signal selector engine a second electrical message indicative of the quality of the second split signal;
(g) dropping from transmission one of the first or the second split signal that was evaluated to be of lesser quality than the other of the split signals;
(h) generating and transmitting from the signal selector to an alarm indicator signal generator an electrical message indicative that both signals are unacceptable;
(i) generating and transmitting from the alarm indicator signal generator to the signal selector an optical message if both signals are of unacceptable quality; and
(j) continuing with the transmission of the other of the first or the second split signals that was indicated to be of higher quality than the other of the split signals.
2. The method for the selection of optical signal quality for the transmission of data as claimed in claim 1, further comprising the steps of providing to the signal selector an indicator of a lack of an active input optical signal if no active signal exists.
3. The method for the selection of optical signal quality for the transmission of data as claimed in claim 1, further comprising the steps of connecting the first split signal through a first switch fabric and the second split signal through a second switch fabric.
4. A method for the selection of optical signal quality for the transmission of data, comprising the steps of
(a) evaluating the quality of a first optical signal and a second optical signal respectively in a first and a second optical performance monitor;
(b) generating and transmitting from each optical performance monitor to a signal selector circuit a first and a second electrical message indicative of the quality of the first optical signal and the second optical signal respectively;
(c) generating and transmitting from the signal selector circuit to an alarm indicator signal generator an electrical message indicative of the quality of the first optical signal and the second optical signal;
(d) generating and transmitting from the alarm indicator signal generator to the signal selector circuit an optical message indicative of a failure if both the first and the second optical signals are evaluated to be unacceptable;
(e) transmitting a selected one of the first optical signal or the second optical signal if at least one of the first and second optical signals is acceptable.
5. The method for the selection of optical signal quality for the transmission of data as claimed in claim 4, further comprising the steps of providing to the signal selector an indicator of a lack of an active input optical signal if no active signal exists.
6. The method for the selection of optical signal quality for the transmission of data as claimed in claim 5, further comprising the step of connecting the first optical signal and the second optical signal through respective switch fabrics.
7. A method for the selection of optical signal quality for the transmission of data, comprising the steps of:
(a) if a first optical performance monitor determines that a first optical signal has failed, and a second performance monitor determines that a second optical signal has failed, activating an alarm indicator signal;
(b) if the first optical performance monitor determines that the first optical signal has failed, and the second performance monitor determines that the second optical signal has not failed, selecting the second optical signal for transmission; and
(c) if the first optical performance monitor determines that the first optical signal is acceptable and the second optical performance monitor determines that the second optical signal is acceptable, selecting the first optical signal for transmission.
8. A method for the selection of optical signal quality for the transmission of data, comprising the steps of:
(a) if a first optical performance monitor determines that a first optical signal has not become degraded, and a second performance monitor determines that a second optical signal has not become degraded, selecting the second optical signal for transmission;
(b) if the first optical performance monitor determines that the first optical signal has not become degraded, and the second performance monitor determines that the second optical signal has become degraded, selecting the first optical signal for transmission.
9. Apparatus for the evaluation and selection of an optical signal, comprising:
(a) an optical performance monitor connected for receiving and evaluating an optical signal and for generating and transmitting an electrical signal in response to the quality of the optical signal;
(b) a selector circuit connected for receiving the electrical signal from the optical performance monitor and for comparing the electrical signal with a second electrical relating to the quality of a second optical signal from a second optical performance monitor, the selector circuit thereupon adapted for generating a responsive electrical signal in relation to the comparative quality of the first and second optical signals;
(c) an unequipped signal generator connected to the selector circuit and adapted for receiving the responsive electrical signal from the selector circuit and generating a responsive optical signal therefrom; and
(d) an alarm indicator signal generator connected to the selector circuit and adapted for receiving the responsive electrical signal from the selector circuit and generating a responsive optical signal therefrom.
10. Apparatus for the evaluation and selection of an optical signal, comprising:
at least two optical performance monitors, each for monitoring the quality of a separate one of at least two optical signals, and for transmitting an electrical signal indicative of results of the monitoring;
a selector circuit for receiving the electrical signals from the optical performance monitors, and for determining if either or both of the electrical signals indicates that one of the optical signals has a quality less than acceptable;
transmitting an optical alarm signal if both of the optical signals have a quality less than acceptable;
if no active signal transmission is involved, generating and transmitting an idle signal.
11. The apparatus of claim 10 further comprising means within the selector circuit for examining the electrical message and for selecting one of the optical signals for transmission if either of the optical signals has a quality equal to or greater than an acceptable value.
12. A method for detecting a fault in an optical signal comprising the steps of transmitting a first optical signal to a performance monitor for monitoring;
if the performance monitor indicates a fault, communicating via an electrical signal indicating the fault; and
receiving the electrical signal and transmitting a second optical signal indicating the fault.
13. The method of claim 12 wherein the step of receiving the electrical signal and transmitting a second optical signal further includes a step of transmitting a second electrical signal to an alarm generator.
14. The method of claim 12, further comprising the step of transmitting an idle signal if no active optical signal is being transmitted.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus including a DCDC converter comprising:
an output stage comprising a pair of output power transistors; and
a gate driver in communication with at least a first of the pair of output power transistors and configured to step to discrete intermediate voltage levels before reaching a final voltage value.
2. The apparatus of claim 1, wherein the gate driver comprises decoupling capacitors.
3. The apparatus of claim 2, wherein the decoupling capacitors comprise series connected capacitors.
4. The apparatus of claim 2, wherein the gate driver further comprises a voltage divider.
5. The apparatus of claim 4, wherein the voltage divider comprises a resistive voltage divider.
6. The apparatus of claim 5, wherein at least one of the decoupling capacitors is coupled in parallel with at least one resistor of the resistive voltage divider.
7. The apparatus of claim 1, wherein the first of the pair of output power transistors comprises multiple parallel transistors.
8. The apparatus of claim 7, wherein a second of the pair of output power transistors comprises multiple parallel transistors.
9. The apparatus of claim 1, further comprising a voltage detector to control provision of the discrete intermediate voltage levels.
10. The apparatus of claim 9, wherein the gate driver comprises first and second multi-level controllers, the voltage detector comprises a first voltage detector responsive to a first potential difference between a source and a drain of the first of the pair of output power transistors, and the apparatus further comprises:
a second voltage detector responsive to a second potential difference between a source and a drain of a second of the pair of output power transistors;
a first switch assembly controller responsive to the first voltage detector and in communication with the first multi-level controller; and
a second switch assembly controller responsive to the second voltage detector and in communication with the second multi-level controller.
11. The apparatus of claim 1, wherein the gate driver comprises first and second gate drivers configured to begin turning on a second of the pair of output power transistors before the final voltage value is reached when the first of the pair output power transistors is being turned off.
12. An apparatus including a DCDC converter comprising:
first and second opposite switching means for providing output power; and
means for driving the switching means including means for stepping to discrete intermediate voltage levels before reaching a final voltage value.
13. The apparatus of claim 12, wherein the means for driving comprises decoupling capacitive means for providing transient current to the switching means.
14. The apparatus of claim 13, wherein the decoupling capacitive means comprise series-connected decoupling capacitive means.
15. The apparatus of claim 13, wherein the means for driving comprises voltage divider means for providing the discrete intermediate voltage levels.
16. The apparatus of claim 15, wherein the voltage divider means comprises resistive voltage divider means for providing the discrete intermediate voltage levels.
17. The apparatus of claim 16, further comprising means for connecting the decoupling capacitive means with the resistive voltage divider means in parallel.
18. The apparatus of claim 12, wherein the first opposite switching means comprises multiple, discrete, parallel switching means for providing output power.
19. The apparatus of claim 18, wherein the second opposite switching means comprises multiple, discrete, parallel switching means for providing output power.
20. The apparatus of claim 12, further comprising voltage detecting means for controlling provision of the discrete intermediate voltage levels.
21. The apparatus of claim 20, wherein the means for driving comprises first and second multi-level controller means for driving the first and second opposite switching means, respectively, the voltage detecting means comprises means for detecting a first potential difference between a source and a drain of the first opposite switching means, and the apparatus further comprises:
means for detecting a second potential difference between a source and a drain of the second opposite switching means;
means for controlling the first multi-level controller means based on the first potential difference; and
means for controlling the second multi-level controller means based on the second potential difference.
22. The apparatus of claim 12, wherein the means for driving comprises means for beginning turn on of the second opposite switching means before the final voltage value is reached for the first opposite switching means when the first opposite switching means is being turned off.
23. A method comprising:
providing output power with an output stage of a DCDC converter, the output stage comprising a pair of output power transistors; and
driving at least a first of the pair of output power transistors by stepping to discrete intermediate voltage levels before reaching a final voltage value.
24. The method of claim 23, further comprising providing transient current to the first of the pair of the output power transistors using decoupling capacitors.
25. The method of claim 24, wherein providing the transient current comprises using series connected decoupling capacitors.
26. The method of claim 24, further comprising using a voltage divider to provide the discrete intermediate voltage levels.
27. The method of claim 26, wherein using the voltage divider comprises using a resistive voltage divider.
28. The method of claim 27, wherein providing the transient current comprises using at least one of the decoupling capacitors coupled in parallel with at least one resistor of the resistive voltage divider.
29. The method of claim 23, wherein providing the output power comprises using the first of the pair of output power transistors comprising multiple parallel transistors.
30. The method of claim 29, wherein providing the output power comprises using a second of the pair of output power transistors comprising multiple parallel transistors.
31. The method of claim 23, further comprising controlling provision of the discrete intermediate voltage levels based on voltage detection.
32. The method of claim 31, wherein said driving comprises driving the first of the pair of output power transistors using a first multi-level controller and driving a second of the pair of output power transistors using a second multi-level controller, and controlling the provision of the discrete intermediate voltage levels comprises:
detecting a first potential difference between a source and a drain of the first of the pair of output power transistors;
controlling the first multi-level controller based on the first potential difference;
detecting a second potential difference between a source and a drain of a second of the pair of output power transistors; and
controlling the second multi-level controller based on the second potential difference.
33. The method of claim 23, wherein said driving comprises beginning turn on of a second of the pair of output power transistors before the final voltage value is reached when the first of the pair of output power transistors is being turned off.
34. A method of direct current to direct current power conversion, the method comprising:
generating a first output voltage at an output of a first switch; and
generating a second output voltage at an output of a second switch, the output of the first switch in communication with the output of the second switch,
wherein generating the first output voltage comprises turning on the first switch by selectively applying N>2 different voltages to a control terminal of the first switch, and
wherein generating the second output voltage comprises turning on the second switch by selectively applying M>1 different voltages to a control terminal of the second switch.
35. The method of claim 34, wherein M is greater than two.
36. The method of claim 34, wherein the outputs of the first and second switches are in communication with a load.
37. The method of claim 36, wherein the outputs of the first and second switches are in communication with the load via an inductor and a capacitor.
38. The method of claim 34, further comprising supplying each of the N different voltages with respective N voltage sources.
39. The method of claim 34, wherein the first switch comprises a transistor having a source and a drain, and the method further comprises detecting a potential difference between the source and the drain.
40. The method of claim 39, further comprising selectively applying the N different voltages to the control terminal of the first switch in response to the detected potential difference.
41. The method of claim 34, wherein said generating the first output voltage and generating the second output voltage comprises alternately turning on the first and second switches using first and second multi-level controllers.
42. The method of claim 34, further comprising providing transient current through N decoupling capacitors.
43. The method of claim 42, wherein said providing transient current comprises employing at least one external capacitor, the at least one external capacitor being of the N decoupling capacitors and being external to an integrated circuit comprising the first and second switches.